[AP4201]

015008157-E-00

- 12 -

2015/09

CSB

SCK

TxD

RxD

tSCKH

tSCKP

tSCKW

tSCKW

tDIS

tDIH

Hi-Z

“H”

“L”

tPD

tPD

CSB

SCK

TxD

RxD

tOZ

tCSH

SCK, CSB, TxD

0.8 VDC

tSCR

tSCF

0.2 VDC

Figure 3. SCI Interface Timing Chart 2

Table 2. Serial F/F Control Timing

Parameter

Symbol

min

typ

max

Unit

Condition

CLK Period

100

-

-

ns

CLK Pulse Width

40

-

-

ns

Data Set-up Time

25

-

-

ns

Data Hold Time

40

-

-

ns

LAT Pulse Width

2

-

-

μs

The AC timings of CLK (SCK), LAT (CSB), SI (TxD) and SO (RxD) are the same as the SCI interface except

CLK

LAT

Figure 4. Serial F/F Control timing