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ADF5355

Data Sheet

RF SYNTHESIZER—A WORKED EXAMPLE

Use the following equations to program the ADF5355 synthesizer:

(

)

Divider

MOD1

MOD2

FRAC2

FRAC1

INT

PFD

OUT

(7)

where:

RFOUT is the RF output frequency.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality.

MOD1 is the fixed 24-bit modulus.

MOD2 is the auxiliary modulus.

RF Divider is the output divider that divides down the VCO

frequency.

fPFD = REFIN × ((1 + D)/(R × (1 + T)))

(8)

where:

REFIN is the reference frequency input.

D is the REFIN doubler bit.

R is the REF reference division factor.

T is the reference divide by 2 bit (0 or 1).

For example, in a universal mobile telecommunication system

(UMTS) where a 2112.8 MHz RF frequency output (RFOUT) is

required, a 122.88 MHz reference frequency input (REFIN)

is available. Note that the ADF5355 VCO operates in the

frequency range of 3.4 GHz to 6.8 GHz. Therefore, the RF divider

of 2 must be used (VCO frequency = 4225.6 MHz, RFOUT =

VCO frequency/RF divider = 4225.6 MHz/2 = 2112.8 MHz).

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 54).

In this example, the 122.88 MHz reference signal is divided by 2

to generate fPFD of 61.44 MHz. The desired channel spacing is

200 kHz.

Figure 54. Loop Closed Before Output Divider

The worked example follows:

•

N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =

68.7760416666666667

•

INT = int(VCO frequency/fPFD) = 68

•

FRAC = 0.7760416666666667

•

MOD1 = 16,777,216

•

FRAC1 = int(MOD1 × FRAC) = 13019818

•

Remainder = 0.6666666667 or 2/3

•

MOD2 = fPFD/GCD(fPFD, fCHSP) =

61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536

•

FRAC2 = Remainder × 1536 = 1024

From Equation 8,

fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz

2112.8 MHz = 61.44 MHz × ((I

NT + (FRAC1 +

FRAC2/MOD2)/224))/2

(9)

where:

INT = 68

FRAC1 = 13,019,817

MOD2 = 1536

FRAC2 = 1024

RF Divider = 2

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system, increase the PFD frequency. Doubling the PFD

frequency typically improves noise performance by 3 dB.

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals;

however, these bandwidths typically have a long lock time. A

wider loop bandwidth achieves faster lock times but may lead

to increased spurious signals inside the loop bandwidth.

OPTIMIZING JITTER

For lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of in-band noise from

the PLL. Set the PLL filter bandwidth such that the in-band noise

of the PLL intersects with the open-loop noise of the VCO,

minimizing the contribution of both to the overall noise.

Use the ADIsimPLL design tool for this task.

fPFD

PFD

VCO

DIVIDER

÷2

RFOUT

Rev. A | Page 34 of 38

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