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ADF5355 Datasheet(PDF) 36 Page - Analog Devices |
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ADF5355 Datasheet(HTML) 36 Page - Analog Devices |
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36 / 38 page  ADF5355 Data Sheet APPLICATIONS INFORMATION POWER SUPPLIES The ADF5355 contains four multiband VCOs that together cover an octave range of frequencies. To ensure best performance, it is vital to connect a low noise regulator, such as the ADM7150, to the VVCO pin. Connect the same regulator to VVCO, VREGVCO, and VP. For the 3.3 V supply pins, use one or two ADM7150 regulators. Figure 55 shows the recommended connections. PRINTED CIRCUIT BOARD (PCB) DESIGN GUIDELINES FOR A CHIP-SCALE PACKAGE The lands on the 32-lead lead frame chip-scale package are rectangular. The PCB pad for these lands must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. Center each land on the pad to maximize the solder joint size. The bottom of the chip-scale package has a central exposed thermal pad. The thermal pad on the PCB must be at least as large as the exposed pad. On the PCB, there must be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern. This clearance ensures the avoidance of shorting. To improve the thermal performance of the package, use thermal vias on the PCB thermal pad. If vias are used, incorporate them into the thermal pad at the 1.2 mm pitch grid. The via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with 1 oz. of copper to plug the via. For a microwave PLL and VCO synthesizer, such as the ADF5355, take care with the board stack-up and layout. Do not consider using FR4 material because it is too lossy above 3 GHz. Instead, Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is suitable. Take care with the RF output traces to minimize discontinuities and ensure the best signal integrity. Via placement and grounding are critical. Figure 55. ADF5355 Power Supplies 33nF 6800pF 1µF 430 Ω 68 Ω ADF5355 VVCO CPGND AGND RFOUTB CPOUT 1nF 1nF 4.7k Ω RSET LE DATA CLK REFINA FREFIN VTUNE DVDD AVDD CE MUXOUT 16 27 17 29 1 2 3 22 8 31 9 13 18 21 LOCK DETECT AGNDVCO AGNDRF 14 15 19 23 24 25 30 10 20 7 PDBRF 26 SDGND VREGVCO VBIAS VREF 6 32 CREG1 VP 10pF 0.1µF 10pF 0.1µF 10pF 0.1µF 4 RFOUTA– RFOUTA+ 12 11 7.5nH 7.5nH 1nF 1nF COUT 1µF CIN 1µF VOUT = 5.0V VIN = 6.0V VOUT REF VIN GND EN OFF ON VOUT ADM7150 REF_SENSE CBYP 1µF CREG 10µF BYP VREG VRF 100nF 100nF CREG2 REFINB 1nF 1nF FREFIN 28 10pF COUT 1µF CIN 1µF VOUT = 3.3V VIN = 6.0V VOUT REF VIN GND EN OFF ON ADM7150 REF_SENSE CBYP 1µF CREG 10µF BYP VREG 5 AVDD 100 Ω Rev. A | Page 36 of 38 |
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