DLPC3433 datasheet(45/62 Pages) TI1

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500 ms Min

PLL_REFCLK may be active

before power is applied.

HOST_IRQ is driven high when

power and RESETZ are applied to

indicate the DPP343x is not ready for

operation, and then is driven low after

initialization is complete.

0 µs Min

0 µs

Max

PARKZ must be set low a

minimum of 32 µs before any

power is removed (except

VDDLP12), before PLL_REFCLK

is stopped and before RESETZ is

asserted low to allow time for the

DMD mirrors to be parked.

0 µs Min

5 ms Min

PLL_REFCLK must become stable within

5 ms of all power being applied (for

external oscillator application this is

oscillator dependent and for crystal

applications this is crystal and ASIC

oscillator cell dependent).

I2C access can start immediately

after HOST_IRQ goes low (this

should occur within 500 ms from the

release of RESETZ)

HOST_IRQ is pulled high

immediately after RESETZ is

asserted low.

PARKZ

PLL_REFCLK

RESETZ

I2C (activity)

HOST_IRQ

VDD_PLLM/D (1.1 V)

VDD (1.1 V)

VCC18 (1.8 V)

VDDLP12 (if not tied to VDD)

Point at which all supplies reach 95% of

their specified nominal values.

PARKZ must be set high a minimum

of 0 µs before RESETZ is released to

support auto-initialization.

PROJ_ON input

(GPIO_8)

VCC_INTF (1.8 to 3.3 V)

VCC_FLSH (1.8 to 3.3 V)

I2C activity should cease

immediately upon active low

assertion of PARKZ.

0 µs

Min

VCC18 must remain ON long

enough to satisfy DMD power

sequencing requirements defined

in the DLPA2000 specification.

32 µs Min

0 µs

Min

DLPC3433, DLPC3438

www.ti.com

DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016

System Power-Up and Power-Down Sequence (continued)

Figure 24. DLPC343x Power-Up / PARKZ = 0 initiated Fast PARK and Power-Down

10.2 DLPC343x Power-Up Initialization Sequence

It is assumed that an external power monitor will hold the DLPC343x in system reset during power-up. It must do

this by driving RESETZ to a logic low state. It should continue to assert system reset until all ASIC voltages have

reached minimum specified voltage levels, PARKZ is asserted high, and input clocks are stable. During this time,

most ASIC outputs will be driven to an inactive state and all bidirectional signals will be configured as inputs to

avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated. These include LED_SEL_0,

LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0 (see RESETZ pin description for full signal descriptions in Pin

Configuration and Functions. After power is stable and the PLL_REFCLK_I clock input to the DLPC343x is

stable, then RESETZ should be deactivated (set to a logic high). The DLPC343x then performs a power-up

initialization routine that first locks its PLL followed by loading self configuration data from the external flash.

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