1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

OUT2P

OUT2N

V

CC

SENSE

RMI

VTH

CPWM

FG

OUT1P

OUT1N

SGND

5VREG

S-S

CT

IN+

IN–

TMP815

www.ti.com

SLDS153B – MAY 2009 – REVISED NOVEMBER 2015

5 Pin Configuration and Functions

PW Package

16-Pin TSSOP

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

OUT2P

1

O

Upper-side driver output

OUT2N

2

O

Lower-side driver output

Power supply

For the power stabilization capacitor on the signal side (see *2 in Figure 5), use the capacitance

of 1

3

For the power stabilization capacitor on the power side (see *3 in Figure 5), use the capacitance

of 1

μF or more. Connect the power supply on the power side and GND with a thick and short

pattern.

Current limiting detection (see *8 in Figure 5)

SENSE

4

I

When the pin voltage exceeds 0.2 V, the current is limited, and the operation enters the lower

regeneration mode. Connect to GND if not used.

Minimum speed setting (see *6 in Figure 5)

If the device power supply is likely to be turned off first when the pin is used with external power

RMI

5

I

supply, insert a current limiting resistor to prevent inflow of large current (also applies to VTH

terminal). Connect to 5VREG with a pullup resistor if not used.

Speed control (see *7 in Figure 5)

For control with pulse input, insert a current limiting resistor and use the pin with a frequency of

VTH

6

I

20 kHz to 100 kHz (TI recommends 20 kHz to 50 kHz). For the control method, see Figure 2.

Connect to GND if not used (at full speed).

Connection to capacitor for generation of PWM basic frequency (see *5 in Figure 5)

CP = 220 pF causes oscillation at f = 30 kHz, which is the basic frequency of PWM. As this is

CPWM

7

O

also used for the current limiting canceling signal, be sure to connect the capacitor even when

speed control is not used.

Rotation speed detection pin (see *9 in Figure 5)

FG

8

O

This is an open-collector output, which can detect the rotation speed from the FG output

according to the phase change over. Keep this pin open when not used.

IN–

9

I

Hall input (see *4 in Figure 5)

Hall input. Make connecting traces as short as possible to prevent carrying of noise. To further

limit noise, insert a capacitor between IN+ and IN–. The Hall input circuit is a comparator having

IN+

10

I

a hysteresis of 15 mV. Also includes a soft-switch section with ±30-mV input-signal differential

Connection to the lock detection capacitor (see *10 in Figure 5)

The constant current charge and discharge circuits cause locking when the pin voltage rises to

CT

11

O

3 V and unlocking when pin voltage falls to 1.1 V. Connect to GND when not used (when locking

is not necessary).

Connection to the soft-start setting capacitor (see *11 in Figure 5)

S-S

12

I

Connect the capacitor between S-S and 5VREG to set the soft-start time, according to the

capacitance that is chosen (see Figure 3 and Figure 4). Connect to GND when not used.

5VREG

13

O

5-V regulator output

System ground (see *1 in Figure 5)

SGND

14

Connection to the control-circuit power-supply system

OUT1N

15

O

Lower-side driver output

OUT1P

16

O

Upper-side driver output

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