PEF2015 datasheet(63/84 Pages) INFINEON

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PEF 2015

Registers Summary

Semiconductor Group

12.97

4.2.6.4

Command Register (CMDR)

Access in demultiplexed

µP-interface mode:

write

address: DH

OMDR:RBS = 0

Access in multiplexed

µP-interface mode:

write

address: 1AH

Reset value: 00H

Writing a logical 1 to a CMDR-register bit starts the respective operation.

Start Timer.

0… no action. If the timer shall be stopped, the TIMR-register must simply be

written with a random value.

1… starts the timer to run cyclically from 0 to the value programmed in

TIMR:TVAL6..0.

TIG

Timer Interrupt Generation.

0… setting the TIG-bit to logical 0 together with the CMDR:ST-bit set to

logical 1 disables the interrupt generation.

1… setting the TIG-bit to logical 1 together with CMDR:ST-bit set to logical 1

causes the MICO to generate a periodic interrupt (ISTA:TIN) each time

the timer expires.

CFR

CIFIFO Reset.

0… no action.

1… resets the signaling FIFO within 2 RCL-periods, i.e. all entries and the

ISTA:SFI-bit are cleared.

MFT1..0

MF-channel Transfer Control Bits 1,0; these bits start the monitor transfer

enabling the contents of the MFFIFO to be exchanged with the subscriber

circuits as specified in MFSAR. The function of some commands depends

furthermore on the selected protocol (OMDR:MFPS). Table 5 summarizes all

available MF-commands.

MFSO

MF-channel Search On.

0… no action.

1… the MICO starts to search for active MF-channels. Active channels are

characterized by an active MX-bit (logical 0) sent by the remote

transmitter. If such a channel is found, the corresponding address is

stored in MFAIR and an ISTA:MAC-interrupt is generated. The search is

stopped when an active MF-channel has been found or when

OMDR:OMS0 is set to 0.

bit 7

bit 0

TIG

CFR

MFT1

MFT0

MFSO

MFFR

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