PEF2015 datasheet(29/84 Pages) INFINEON

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PEF 2015

Operational Description

Semiconductor Group

12.97

3.5

Initialization Procedure

For proper initialization of the MICO the following procedure is recommended:

3.5.1

Hardware Reset

A reset pulse can be applied at the RES-pin for at least 4 PDC-clock cycles. The reset

pulse sets all registers to their reset values (refer to section 4.1).

Note that in this state DCL and FSC do not deliver any clock signals.

3.5.2

MICO Initialization

3.5.2.1

The PCM- and CFI-configuration registers (PMOD, PBNR,

…, CMD1, CMD2, …) should

be programmed to the values required for the application. The correct setting of the

PCM- and CFI-registers is important in order to obtain a reference clock (RCL) which is

consistent with the externally applied clock signals.

The state of the operation mode (OMDR:OMS1..0 bits) does not matter for this

programming step.

PMOD =

PCM-mode, timing characteristics, etc.

PBNR

Number of bits per PCM-frame

POFD

PCM-offset downstream

POFU

PCM-offset upstream

PCSR

PCM-timing

CMD1

CFI-mode, timing characteristics, etc.

CMD2

CFI-timing

CBNR

Number of bits per CFI-frame

CTAR

CFI-offset (time slots)

CBSR

CFI-offset (bits)

CSCR

CFI-sub channel positions

3.5.2.2

Control Memory Reset

Since the hardware reset does not affect the MICO memories (Control and Data

Memories), it is mandatory to perform a "software reset" of the CM. The CM-code '0000'

(unassigned channel) should be written to each location of the CM. The data written to

the CM-data field is then don’t care, e.g. FFH.

OMDR:OMS1..0 must be to '00'B for this procedure (reset value).

MADR

FFH

MACR

70H

Wait for STAR:MAC = 0

The resetting of the complete CM takes 256 RCL-clock cycles. During this time, the

STAR:MAC-bit is set to logical 1.

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