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PEF2015 Datasheet(PDF) 79 Page - Infineon Technologies AG |
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PEF2015 Datasheet(HTML) 79 Page - Infineon Technologies AG |
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79 / 84 page  PEF 2015 Electrical Characteristics Semiconductor Group 79 12.97 PCM and Configurable Interface Timing Parameter Symbol Limit Values Unit Test Conditions min. max. Clock period t CP 240 ns clock frequency ≤ 4096 kHz Clock period low t CPL 80 ns Clock period high t CPH 100 ns Clock period t CP 120 ns clock frequency > 4096 kHz Clock period low t CPL 50 ns Clock period high t CPH 50 ns Frame set-up time to clock t FS 25 ns Frame hold time from clock t FH 50 ns Data clock delay t DCD 125 ns Serial data input set-up time t S 7ns PCM-input data frequency > 4096 kbit/s Serial data hold time t H 35 ns Serial data input set-up time t S 15 ns PCM-input data frequency ≤ 4096 kbit/s Serial data hold time t H 55 ns Serial data input set-up time t S 20 ns CFI-input data frequency > 4096 kbit/s Serial data hold time t H 50 ns Serial data input set-up time t S 0ns CFI-input data frequency ≤ 4096 kbit/s Serial data hold time t H 75 ns PCM-serial data output delay t D 55 ns Tristate control delay t T 60 ns CFI-serial data output delay t CDF 65 ns falling clock edge CFI-serial data output delay t CDR – 90 ns rising clock edge |
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