ATMEGA8 datasheet(22/303 Pages) ATMEL

22 / 303 page

ATmega8(L)

2486M–AVR–12/03

Keep the AVR RESET active (low) during periods of insufficient power supply volt-

age. This can be done by enabling the internal Brown-out Detector (BOD). If the

detection level of the internal BOD does not match the needed detection level, an

external low V

CC Reset Protection circuit can be used. If a reset occurs while a write

operation is in progress, the write operation will be completed provided that the

power supply voltage is sufficient.

I/O Memory

The I/O space definition of the ATmega8 is shown in “” on page 282.

All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions, transferring data between the 32 general pur-

pose working registers and the I/O space. I/O Registers within the address range 0x00 -

0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers,

the value of single bits can be checked by using the SBIS and SBIC instructions. Refer

to the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers

as data space using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

ATMEGA8 Datasheet(PDF) 22 Page - ATMEL Corporation