ATMEGA8 datasheet(73/303 Pages) ATMEL

73 / 303 page

ATmega8(L)

2486M–AVR–12/03

Each half period of the external clock applied must be longer than one system clock

cycle to ensure correct sampling. The external clock must be guaranteed to have less

than half the system clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since

the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-

ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,

resonator, and capacitors) tolerances, it is recommended that maximum frequency of an

external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 31. Prescaler for Timer/Counter0 and Timer/Counter1

(1)

Note:

1. The synchronization logic on the input pins (

T1/T0) is shown in Figure 30.

Special Function IO Register –

SFIOR

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be

reset. The bit will be cleared by hardware after the operation is performed. Writing a

zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share

the same prescaler and a reset of this prescaler will affect both timers. This bit will

always be read as zero.

PSR10

Clear

clk

I/O

Synchronization

Bit

–

ACME

PUD

PSR2

PSR10

SFIOR

Read/Write

R/W

Initial Value

ATMEGA8 Datasheet(PDF) 73 Page - ATMEL Corporation