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ATMEGA8 Datasheet(PDF) 71 Page - ATMEL Corporation |
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ATMEGA8 Datasheet(HTML) 71 Page - ATMEL Corporation |
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71 / 303 page  71 ATmega8(L) 2486M–AVR–12/03 Timer/Counter Interrupt Flag Register – TIFR • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (T im er/C o un ter 0 O ve rflo w In ter rup t En ab le ), a n d TO V 0 a re s et (o ne ), the Timer/Counter0 Overflow interrupt is executed. Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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