ATTINY13 datasheet(42/169 Pages) ATMEL

42 / 169 page

ATtiny13

2535B–AVR–01/04

Note that enabling the alternate function of some of the port pins does not affect the use

of the other pins in the port as general digital I/O.

Ports as General Digital

I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 21 shows a

functional description of one I/O-port pin, here generically called Pxn.

Figure 21. General Digital I/O

(1)

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

clk

I/O, SLEEP, and PUD are common to all ports.

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 51, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configured as an output pin. The port pins are tri-stated when

reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is

driven high (one). If PORTxn is written logic zero when the pin is configured as an out-

put pin, the port pin is driven low (zero).

clk

RPx

RRx

RDx

WDx

PUD

SYNCHRONIZER

WDx:

WRITE DDRx

WRx:

WRITE PORTx

RRx:

READ PORTx REGISTER

RPx:

READ PORTx PIN

PUD:

PULLUP DISABLE

clk

I/O:

I/O CLOCK

RDx:

READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

SLEEP

SLEEP:

SLEEP CONTROL

Pxn

I/O

WPx

WRx

WPx:

WRITE PINx REGISTER

ATTINY13 Datasheet(PDF) 42 Page - ATMEL Corporation

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