ATTINY13 datasheet(71/169 Pages) ATMEL

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ATtiny13

2535B–AVR–01/04

executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in

the Timer/Counter Interrupt Flag Register – TIFR0.

• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set

in the Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if

an overflow in Tim er/Counter0 occurs, i.e., w hen the TOV0 bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

Timer/Counter 0 Interrupt Flag

• Bits 7..4, 0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and

the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF0B is

cle are d by w riting a logic one to the flag. When the I-bit in SRE G, OC IE 0B

(Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the

Timer/Counter Compare Match Interrupt is executed.

• Bit 2 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and

the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared

by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0

Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare

Match Interrupt is executed.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0

(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0

Overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 32,

“Waveform Generation Mode Bit Description” on page 68.

Bit

765

–––

–

OCF0B

OCF0A

TOV0

–TIFR0

Read/Write

R/W

Initial Value

000

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