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TUSB3210 Datasheet(PDF) 19 Page - Texas Instruments |
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TUSB3210 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 44 page ![]() 2–7 Table 2–3. EDB and Buffer Allocations in XDATA (Continued) ADDRESS DESCRIPTION FEF7 ↑ (8–bytes) Output endpoint_0 buffer FEF0 (8 bytes) Out ut end oint_0 buffer FEEF TOPBUFF Top of buffer space ↑ Buffers space FD80 STABUFF Start of buffer space 2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) Data transfers between USB, MCU and external devices are defined by an endpoint descriptor block (EDB). Four input and four output EDBs are provided. With the exception of EDB–0 (I/O Endpoint–0), all EDBs are located in SRAM as shown in Table 2–3. Each EDB contains information describing the X and Y buffers. In addition, it provides general status information. Table 2–4 illustrates the EDB entries for EDB–1 to EDB–3. EDB–0 registers will be described separately. Table 2–4. EDB Entries in RAM (n = 1 to 3) Offset ENTRY NAME DESCRIPTION 07 EPSIZXY_n I/O endpoint_n: X/Y buffer size 06 EPBCTY_n I/O endpoint_n: Y byte count 05 EPBBAY_n I/O endpoint_n: Y buffer base address 04 SPARE Not used 03 SPARE Not used 02 EPBCTX_n I/O endpoint_n: X byte count 01 EPBBAX_n I/O endpoint_n: X buffer base address 00 EPCNF_n I/O endpoint_n: configuration 2.4.1 OEPCNF_n: Output Endpoint Configuration (n=1 to 3) 7 6 5 4 3 210 UBME ISO TOGLE DBUF STALL USBIE RSV RSV R/W R/W R/W R/W R/W R/W R/O R/O BIT NAME RESET FUNCTION 1–0 RSV 0 Reserved 2 USBIE x USB interrupt enable on transaction completion. Set/clear by MCU. USBIE = 0 no interrupt USBIE = 1 interrupt on transaction completion 3 STALL 0 USB stall condition indication. Set/clear by MCU. STALL = 0 No stall STALL = 1 USB stall condition. If set by MCU, a STALL handshake is initiated and the bit is cleared by MCU. 4 DBUF x Double buffer enable. Set/clear by MCU. DBUF = 0 Primary buffer only (X–buffer only) DBUF = 1 Toggle bit selects buffer 5 TOGLE x USB Toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1 6 ISO x ISO = 0 Non-isochronous transfer. This bit must be cleared by MCU since only Non-isochronous transfer is supported. 7 UBME x UBM enable/disable bit. Set/clear by MCU. UBME = 0 UBM cannot use this endpoint. UBME = 1 UBM can use this endpoint. |
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