AD8285

Data Sheet

Rev. B | Page 16 of 27

Figure 26. Data and DSYNC Timing

ADC

The AD8285 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 12-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on preceding samples. Sampling occurs on the

rising edge of the clock. The output staging block aligns the data,

corrects errors, and passes the data to the output buffers.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD8285 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled into the CLK+ and CLK− pins via a

transformer or by using capacitors. These pins are biased

internally and require no additional bias.

Figure 27 shows the preferred method for clocking the AD8285.

A low jitter clock source, such as the Valpey Fisher oscillator

VFAC3-BHL-50MHz, is converted from single ended to

differential using an RF transformer. The back to back Schottky

diodes across the secondary transformer limit clock excursions

into the AD8285 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD8285, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

Figure 27. Transformer Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a

differential PECL or LVDS signal to the sample clock input pins

as shown in Figure 28 and Figure 29. The AD9515/AD9520-0

device family of clock drivers offers excellent jitter performance.

Figure 28. Differential PECL Sample Clock

Figure 29. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

drive CLK+ directly from a CMOS gate and bypass the CLK−

pin to ground with a 0.1 μF capacitor in parallel with a 39 kΩ

resistor (see Figure 30). Although the CLK+ input circuit supply

is AVDD18, this input is designed to withstand input voltages of

up to 3.3 V, making the selection of the drive logic voltage very

flexible. The AD9515/AD9520-0 device family can provide 3.3 V

inputs (see Figure 31). In this case, 39 kΩ resistor is not needed.

N

INAx

N + 1

XXXX

NOTES

1. FOR THIS CONFIGURATION, ADDRESS 0x0C, BITS [3:0] IS SET TO 0110 (CHANNEL A, B, C, AND D ENABLED).

2. DSYNC IS ALWAYS ALIGNED WITH CHANNEL A UNLESS CHANNEL A OR CHANNEL AUX IS THE ONLY CHANNEL SELECTED, IN WHICH CASE DSYNC IS NOT ACTIVE.

3. THERE IS A SEVEN-CLOCK CYCLE LATENCY FROM SAMPLING A CHANNEL TO ITS DIGITAL DATA BEING PRESENT ON THE PARALLEL BUS PINS.

OUTB

OUTC

OUTD

OUTB

OUTC

OUTD

CLK–

CLK+

D[11:0]

DSYNC

0.1µF

0.1µF

0.1µF

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω 100Ω

CLK–

CLK+

ADC

AD8285

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

100Ω

0.1µF

0.1µF

0.1µF

0.1µF

240Ω

240Ω

50Ω*

CLK

CLK

*50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8285

PECL DRIVER

3.3V

OUT

VFAC3

AD951x/AD952x

FAMILY

100Ω

0.1µF

0.1µF

0.1µF

0.1µF

AD951x/AD952x

FAMILY

50Ω*

CLK

CLK

*50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8285

LVDS DRIVER

3.3V

OUT

VFAC3