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Data Sheet

AD8285

Rev. B | Page 19 of 27

SERIAL PERIPHERAL INTERFACE (SPI)

The AD8285 serial peripheral interface allows the user to configure

the signal chain for specific functions or operations through a

structured register space provided inside the chip. The SPI offers

added flexibility and customization depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that

can be further divided into fields, as documented in the Memory

Map section. Detailed operational information can be found in

the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI.

Three pins define the serial peripheral interface (SPI): SCLK,

SDIO, and CS. The SCLK (serial clock) pin is used to synchronize

the read and write data presented to the device. The SDIO (serial

data input/output) pin is a dual purpose pin that allows data to

be sent to and read from the internal memory map registers of

the device. The CS (chip select bar) pin is an active low control

that enables or disables the read and write cycles (see Table 7).

Table 7. Serial Port Pins

Function

SCLK

Serial clock. The serial shift clock input. SCLK is used

to synchronize serial interface reads and writes.

SDIO

Serial data input/output. A dual-purpose pin. The

typical role for this pin is as an input or output,

depending on the instruction sent and the relative

position in the timing frame.

Chip select bar (active low). This control gates the

read and write cycles.

The falling edge of the CS in conjunction with the rising edge of

the SCLK determines the start of the framing sequence. During

an instruction phase, a 16-bit instruction is transmitted, followed

by one or more data bytes, which is determined by Bit Field W0

and Bit Field W1. An example of the serial timing and its

definitions can be found in Figure 32 and Table 8.

In normal operation, CS signals to the device that SPI

commands are to be received and processed. When CS is brought

low, the device processes SCLK and SDIO to process instructions.

Normally, CS remains low until the communication cycle is

complete. However, if connected to a slow device, CS can be

brought high between bytes, allowing older microcontrollers

enough time to transfer data into shift registers. CS can be

stalled when transferring one, two, or three bytes of data. When

W0 and W1 are set to 11, the device enters streaming mode and

continues to process data, either reading or writing, until CS is

taken high to end the communication cycle. This allows

complete memory transfers without having to provide

additional instructions.

Regardless of the mode, if CS is taken high in the middle of any

byte transfer, the SPI state machine is reset, and the device waits

for a new instruction.

In addition to the operation modes, the SPI port can be

configured to operate in different modes. For applications that

do not require a control port, the CS line can be tied and held

high. This places the remainder of the SPI pins in their secondary

mode, as is defined in the SDIO Pin section and the SCLK Pin

section. The CS pin can also be tied low to enable 2-wire mode.

When CS is tied low, SCLK and SDIO are the only pins required

for communication. Although the device is synchronized during

power-up, caution must be exercised when using this mode to

ensure that the serial port remains synchronized with the CS line.

When operating in 2-wire mode, it is recommended to use a 1-,

2-, or 3-byte transfer exclusively. Without an active CS line,

streaming mode can be entered but not exited.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip and read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the serial data input/output (SDIO)

pin to change direction from an input to an output at the

appropriate point in the serial frame.

Data can be sent in MSB- or LSB-first mode. MSB-first mode is

the default at power-up and can be changed by adjusting the

configuration register. For more information about this and

other features, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

HARDWARE INTERFACE

The pins described in Table 7 constitute the physical interface

between the programming device of the user and the serial port

of the AD8285. The SCLK and CS pins function as inputs when

using the SPI interface. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during readback.

This interface is flexible enough to be controlled by either serial

PROMs or PIC microcontrollers. This flexibility provides the user

with an alternative method, other than a full SPI controller, for

programming the device (see the AN-812 Application Note).

If the user chooses not to use the SPI interface, these pins serve

a dual function and are associated with secondary functions

when the CS is strapped to AVDD33 during device power-up.

See the SDIO Pin section and SCLK Pin section for details on

which pin strappable functions are supported on the SPI pins.

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