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Data Sheet

AD8285

Rev. B | Page 17 of 27

Figure 30. Single-Ended 1.8 V CMOS Sample Clock

Figure 31. Single-Ended 3.3 V CMOS Sample Clock

CLOCK DUTY CYCLE CONSIDERATIONS

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD8285 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. The DCS allows a wide

range of clock input duty cycles without affecting the performance

of the AD8285.

When the DCS is on, noise and distortion performance are nearly

flat for a wide range of duty cycles. However, some applications

may require the DCS function to be off. If so, keep in mind that the

dynamic range performance can be affected when operating in this

mode. See Table 9 for more information about using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to create

the nonsampling edge. As a result, any changes to the sampling

frequency require approximately eight clock cycles to allow the

DLL to acquire and lock to the new rate.

CLOCK JITTER CONSIDERATIONS

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (fA)

due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]

In this equation, the rms aperture jitter represents the root

mean square of all jitter sources, including the clock input, analog

input signal, and ADC aperture jitter. Intermediate frequency

undersampling applications are particularly sensitive to jitter.

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD8285. Separate power

supplies for clock drivers from the ADC output driver supplies

to avoid modulating the clock signal with digital noise. Low jitter,

crystal-controlled oscillators make the best clock sources, such

as the Valpey Fisher VFAC3 series. If the clock is generated from

another type of source (by gating, dividing, or other methods),

retime it by the original clock during the last step.

Refer to the AN-501 Application Note and the AN-756 Application

Note for more in-depth information about how jitter performance

relates to ADCs.

SDIO PIN

The SDIO pin is required to operate the SPI. It has an internal

30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V

tolerant. If applications require that this pin be driven from a

3.3 V logic level, insert a 1 kΩ resistor in series with this pin to

limit the current.

SCLK PIN

The SCLK pin is required to operate the SPI port interface. It

has an internal 30 kΩ pull-down resistor that pulls this pin low

and is both 1.8 V and 3.3 V tolerant.

CS PIN

The CS pin is required to operate the SPI port interface. It has

an internal 70 kΩ pull-up resistor that pulls this pin high and is

both 1.8 V and 3.3 V tolerant.

RBIAS PIN

To set the internal core bias current of the ADC, place a resistor

nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using

anything other than the recommended 10.0 kΩ resistor for RBIAS

degrades the performance of the device. Therefore, it is imperative

that at least a 1.0% tolerance on this resistor be used to achieve

consistent performance.

0.1µF

39kΩ

1.8V

CMOS DRIVER

50Ω*

OPTIONAL

100Ω

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8285

3.3V

OUT

VFAC3

AD951x/AD952x

FAMILY

0.1µF

CMOS DRIVER

3.3V

50Ω*

OPTIONAL

100Ω

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD8285

3.3V

OUT

VFAC3

0.1µF

AD951x/AD952x

FAMILY

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