Data Sheet

AD8283

Rev. C | Page 5 of 27

DIGITAL SPECIFICATIONS

+105°C, unless otherwise noted.

Table 3.

Temperature

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Full

250

mV p-p

Input Common-Mode Voltage

Full

1.2

V

Input Resistance (Differential)

25°C

20

kΩ

Input Capacitance

25°C

1.5

pF

LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL)

Logic 1 Voltage

Full

1.2

3.6

V

Logic 0 Voltage

Full

0.3

V

Input Resistance

25°C

30

kΩ

Input Capacitance

25°C

0.5

pF

LOGIC INPUT (CS)

Logic 1 Voltage

Full

1.2

3.6

V

Logic 0 Voltage

Full

0.3

V

Input Resistance

25°C

70

kΩ

Input Capacitance

25°C

0.5

pF

LOGIC INPUT (SDIO)

Logic 1 Voltage

Full

1.2

DVDD33x + 0.3

V

Logic 0 Voltage

Full

0

0.3

V

Input Resistance

25°C

30

kΩ

Input Capacitance

25°C

2

pF

Full

3.0

V

Full

0.3

V

LOGIC OUTPUT (D[11:0], DSYNC)

Full

3.0

V

Full

0.05

V

1

See the AN-835 Application Note,UnderstandingHighSpeed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO pins sharing the same connection.