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AD8283

Data Sheet

Rev. C | Page 18 of 27

reference to achieve more accuracy. However, this device does

not support ADC full-scale ranges below 2.0 V p-p.

When applying the decoupling capacitors to the VREF pin, use

ceramic low-ESR capacitors. These capacitors should be close to

the reference pin and on the same layer of the PCB as

the AD8283. The VREF pin should have both a 0.1 µF capacitor

and a 1 µF capacitor connected in parallel to the analog ground.

These capacitor values are recommended for the ADC to

properly settle and acquire the next valid sample.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD8283, it is recommended

that two separate 1.8 V supplies and two separate 3.3 V supplies

be used: one for analog 1.8 V (AVDD18x) and digital 1.8 V

(DVDD18x) and one for analog 3.3 V (AVDD33x) and digital

3.3 V (DVDD33x). If only one supply is available for both analog

and digital, for example, AVDD18x and DVDD18x, it should be

routed to the AVDD18x first and then tapped off and isolated

with a ferrite bead or a filter choke preceded by decoupling

capacitors for the DVDD18x. The same is true for the analog

and digital 3.3 V supplies. The user should employ several

decoupling capacitors on all supplies to cover both high and low

frequencies. These should be located close to the point of entry

at the PC board level and close to the parts, with minimal trace

lengths.

A single PC board ground plane should be sufficient when using

the AD8283. With proper decoupling and smart partitioning of

the PC board’s analog, digital, and clock sections, optimum

performance can be achieved easily.

EXPOSED PADDLE THERMAL HEAT SLUG

RECOMMENDATIONS

It is required that the exposed paddle on the underside of the

device be connected to a quiet analog ground to achieve the

best electrical and thermal performance of the AD8283. An

exposed continuous copper plane on the PCB should mate to

the AD8283 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be filled or plugged with nonconductive epoxy.

To maximize the coverage and adhesion between the device and

PCB, partition the continuous copper pad by overlaying a silk-

screen or solder mask to divide this into several uniform sections.

This ensures several tie points between the two during the reflow

process. Using one continuous plane with no partitions only

guarantees one tie point between the AD8283 and PCB. For

more detailed information on packaging and for more PCB

layout examples, see the AN-772 Application Note.

ADA8282 Datasheet(PDF) 18 Page - Analog Devices

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