AD8283

Data Sheet

Rev. C | Page 16 of 27

N

INAx

N + 1

XXXX

NOTES

1. FOR ABOVE CONFIGURATION REGISTER ADDRESS 0C SET TO 1010 (CHANNEL A, B, C, D, E AND F ENABLED).

2. DSYNC IS ALWAYS ALIGNED WITH CHANNEL A UNLESS CHANNEL A OR CHANNEL AUX IS THE ONLY CHANNEL SELECTED, IN WHICH CASE DSYNC IS NOT ACTIVE.

3. THERE IS A SEVEN CLOCK CYCLE LATENCY FROM SAMPLING A CHANNEL TO ITS DIGITAL DATA BEING PRESENT ON THE PARALLEL BUS PINS.

OUTB

OUTC

OUTD

OUTE

OUTF

OUTB

CLK–

CLK+

D[11:0]

DSYNC

Figure 26. Data and DSYNC Timing

ADC

The AD8283 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 12-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on preceding samples. Sampling occurs on the

rising edge of the clock. The output staging block aligns the

data, corrects errors, and passes the data to the output buffers.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD8283 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or using capacitors. These pins are biased

internally and require no additional bias.

Figure 27 shows the preferred method for clocking the AD8283.

A low jitter clock source, such as the Valpey Fisher oscillator

VFAC3-BHL-50MHz, is converted from single ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD8283 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD8283, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

0.1µF

0.1µF

0.1µF

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω 100Ω

CLK–

CLK+

ADC

AD8283

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

Figure 27. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a

differential PECL or LVDS signal to the sample clock input pins

as shown in and Figure 28 and Figure 29. The AD9515/

AD9520-0 family of clock drivers offers excellent jitter

performance.

100Ω

0.1µF

0.1µF

0.1µF

0.1µF

240Ω

240Ω

CLK

CLK

CLK–

CLK+

ADC

AD8283

PECL DRIVER

3.3V

OUT

VFAC3

AD9515/AD9520-0

Figure 28. Differential PECL Sample Clock

100Ω

0.1µF

0.1µF

0.1µF

0.1µF

AD9515/AD9520-0

CLK

CLK

CLK–

CLK+

ADC

AD8283

LVDS DRIVER

3.3V

OUT

VFAC3

Figure 29. Differential LVDS Sample Clock