ADA8282 datasheet(14/27 Pages) AD

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AD8283

Data Sheet

Rev. C | Page 14 of 27

THEORY OF OPERATION

RADAR RECEIVE PATH AFE

The primary application for the AD8283 is high-speed ramp,

frequency modulated, continuous wave radar (HSR-FMCW

radar). Figure 25 shows a simplified block diagram of an HSR-

FMCW radar system. The signal chain requires multiple

channels, each including a low noise amplifier (LNA), a

programmable gain amplifier (PGA), an antialiasing filter

(AAF), and an analog-to-digital converter (ADC). The AD8283

provides all of these key components in a single 10 × 10 LFCSP

package.

The performance of each component is designed to meet the

demands of an HSR-FMCW radar system. Some examples of

these performance metrics are the LNA noise, PGA gain range,

AAF cutoff characteristics, and ADC sample rate and

resolution.

The AD8283 includes a multiplexer (mux) in front of the ADC

as a cost saving alternative to having an ADC for each channel.

The mux automatically switches between each active channel

after each ADC sample. The DSYNC output indicates when

Channel A data is at the ADC output, and data for each active

channel follows sequentially with each clock cycle.

The effective sample rate for each channel is reduced by a factor

equal to the number of active channels. The ADC resolution of

12 bits with up to 72 MSPS sampling satisfies the requirements

for most HSR-FMCW approaches.

DSP

ANTENNA

VCO

12-BIT

ADC

AAF

PGA

LNA

PGA

LNA

PGA

LNA

AD8283

MUX

REF.

OSCILLATOR

CHIRP RAMP

GENERATOR

Figure 24. Radar System Overview

MUX

AD8283

MUX

CONTROLLER

SPI

INTERFACE

SDIO

SCLK

AAF

PGA

LNA

PIPELINE

ADC

THIRD-ORDER

ELLIPTICAL FILTER

–6dB,

0dB,

6dB,

12dB

12-BIT

72MSPS

INx+

INx–

22dB

200Ω/

200kΩ

PARALLEL

3.3V CMOS

D11:D0

DSYNC

Figure 25. Simplified Block Diagram of a Single Channel

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