ADuC7122BBCZ datasheet(53/96 Pages) AD

53 / 96 page

Data Sheet

ADuC7122

Table 85. GPxPAR Register

Name

Address

Default Value

Access

GP0PAR

0xFFFF0D2C

0x20000000

R/W

GP1PAR

0xFFFF0D3C

0x00000000

R/W

GP2PAR

0xFFFF0D4C

0x00000000

R/W

GP3PAR

0xFFFF0D5C

0x00222222

R/W

GPxPAR programs the parameters for Port 0, Port 1, Port 2, and

Port 3. Note that the GPxDAT MMR must always be written

after changing the GPxPAR MMR.

Table 86. GPxPAR MMR Bit Designations

Bit

Description

31:29

Reserved

Pull-up disable Px.7 pin

27:25

Reserved

Pull-up disable Px.6 pin

23:21

Reserved

Pull-up disable Px.5 pin

19:17

Reserved

Pull-up disable Px.4 pin

15:13

Reserved

Pull-up disable Px.3 pin

11:9

Reserved

Pull-up disable Px.2 pin

7:5

Reserved

Pull-up disable Px.1 pin

3:1

Reserved

Pull-up disable Px.0 pin

Table 87. GPxDAT Register

Name

Address

Default Value

Access

GP0DAT

0xFFFF0D20

0x000000XX

R/W

GP1DAT

0xFFFF0D30

0x000000XX

R/W

GP2DAT

0xFFFF0D40

0x000000XX

R/W

GP3DAT

0xFFFF0D50

0x000000XX

R/W

GPxDAT is a Port x configuration and data register. It configures

the direction of the GPIO pins of Port x, sets the output value

for the pins configured as outputs, and receives and stores the

input value of the pins configured as inputs.

Table 88. GPxDAT MMR Bit Designations

Bit

Description

31:24

Direction of the data.

Set to 1 by the user to configure the GPIO pin as an output.

Cleared to 0 by user to configure the GPIO pin as an input.

23:16

Port x data output.

15:8

Reflect the state of Port x pins at reset (read only).

7:0

Port x data input (read only).

Table 89. GPxSET Register

Name

Address

Default Value

Access

GP0SET

0xFFFF0D24

0x000000XX

GP1SET

0xFFFF0D34

0x000000XX

GP2SET

0xFFFF0D44

0x000000XX

GP3SET

0xFFFF0D54

0x000000XX

Table 90. GPxSET MMR Bit Designations

Bit

Description

31: 24

Reserved.

23:16

Data Port x set bit.

Set to 1 by the user to set bit on Port x; also sets the

corresponding bit in the GPxDAT MMR.

Cleared to 0 by the user; does not affect the data output.

15: 0

Reserved.

GPxSET is a data set Port x register.

Table 91. GPxCLR Register

Name

Address

Default Value

Access

GP0CLR

0xFFFF0D28

0x000000XX

GP1CLR

0xFFFF0D38

0x000000XX

GP2CLR

0xFFFF0D48

0x000000XX

GP3CLR

0xFFFF0D58

0x000000XX

GPxCLR is a data clear Port x register.

Table 92. GPxCLR MMR Bit Designations

Bit

Description

31:24

Reserved.

23:16

Data Port x clear bit.

Set to 1 by the user to clear bit on Port x; also clears

the corresponding bit in the GPxDAT MMR.

Cleared to 0 by the user; does not affect the data

output.

15:0

Reserved.

Open-collector functionality is available on the following GPIO

pins: P1.7, P1.6, P2.x, and P3.x. Open-collector functionality can be

configured using GP1OCE[7:6], GP2OCE[7:0], and GP3OCE[7:0].

Table 93. GPxOCE MMR Bit Designations

Bit

Description

31:8

Reserved.

GPIO Px.7 open-collector enable