ADuC7122BBCZ datasheet(27/96 Pages) AD

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Data Sheet

ADuC7122

ADC CIRCUIT OVERVIEW

The analog-to-digital converter (ADC) incorporates a fast,

multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V

supplies and is capable of providing a throughput of up to 1 MSPS

when the clock source is 41.78 MHz. This block provides the

user with a multichannel multiplexer, differential track-and-

hold, on-chip reference, and ADC.

The ADC consists of a 12-bit successive approximation converter

based around two capacitor DACs. Depending on the input

signal configuration, the ADC can operate in one of the

following three modes:

•

Fully differential mode for small and balanced signals

•

Single-ended mode for any single-ended signals

•

Pseudo differential mode for any single-ended signals,

taking advantage of the common-mode rejection offered

by the pseudo differential input

The converter accepts an analog input range of 0 to VREF when

operating in single-ended mode or pseudo differential mode. In

fully differential mode, the input signal must be balanced around

a common-mode voltage, VCM, in the range 0 V to AVDD, and

with maximum amplitude of 2 VREF (see Figure 12).

AVDD

VCM

2VREF

Figure 12. Examples of Balanced Signals for Fully Differential Mode

A high precision, low drift, and factory-calibrated 2.5 V reference

is provided on chip. An external reference can also be connected

as described in the Band Gap Reference section.

Single or continuous conversion modes can be initiated in

software. An external

CONVSTEE

pin, an output generated from

the on-chip PLA, or a Timer0 or Timer1 overflow can also be

used to generate a repetitive trigger for ADC conversions.

If the signal has not been deasserted by the time the ADC

conversion is complete, a second conversion begins

automatically.

A voltage output from an on-chip band gap reference propor-

tional to absolute temperature can also be routed through the

front-end ADC multiplexer, effectively an additional ADC

channel input. This facilitates an internal temperature sensor

channel, measuring die temperature to an accuracy of ±3°C.

For the ADuC7122, a number of modifications have been made

to the ADC input structure that appears in the ADuC702x

family.

The PADC0 and PADC1 inputs connect to a PGA in pseudo

differential mode and allow for selectable gains from 1 to 5 with

32 steps. The remaining ADC channels can be configured as

single, differential, or pseudo differential. A buffer is provided

before the ADC for measuring internal channels.

Rev. A | Page 27 of 96

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