ADuC7122BBCZ datasheet(63/96 Pages) AD

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Data Sheet

ADuC7122

I2C Address 0 Register

Name:

I2C0ADR0, I2C1ADR0

Address:

0xFFFF0898, 0xFFFF0918

Default Value: 0x00, 0x00

Access:

Read/write

Function:

This 8-bit MMR holds the 7-bit slave address +

the read/write bit when the master begins

communicating with a slave.

I2C Address 1 Register

Name:

I2C0ADR1, I2C1ADR1

Address:

0xFFFF089C, 0xFFFF091C

Default Value: 0x00, 0x00

Access:

Read/write

Function:

This 8-bit MMR is used in 10-bit addressing

mode only. This register contains the least

significant byte of the address.

I2C Master Clock Control Register

Name:

I2C0DIV, I2C1DIV

Address:

0xFFFF08A4, 0xFFFF0924

Default Value: 0x1F1F, 0x1F1F

Access:

Read/write

Function:

This MMR controls the frequency of the I2C

clock generated by the master on to the SCL

pin. For further details, see the I2C section.

I2C Start Byte Register

Name:

I2C0SBYTE, I2C1SBYTE

Address:

0xFFFF08A0, 0xFFFF0920

Default Value: 0x00, 0x00

Access:

Read/write

Function:

This MMR can be used to generate a start byte

at the start of a transaction.

To generate a start byte followed by a normal address, first write

to I2CxSBYTE, then write to the address register (I2CxADRx).

This drives the byte written in I2CxSBYTE onto the bus fol-

lowed by a repeated start. This register can be used to drive any

byte onto the I2C bus followed by a repeated start (not a start

byte only, for example, 00000001).

Table 104. I2CxADR0 MMR in 7-Bit Address Mode (Address = 0xFFFF0898, 0xFFFF0918, Default Value = 0x00)

Bit

Name

Description

7:1

I2CADR

These bits contain the 7-bit address of the required slave device.

R/W

Bit 0 is the read/write bit.

When this bit = 1, a read sequence is requested.

When this bit = 0, a write sequence is requested.

Table 105. I2CxADR0 MMR in 10-Bit Address Mode

Bit

Name

Description

7:3

These bits must be set to [11110b] in 10-bit address mode.

2:1

I2CMADR

These bits contain ADDR[9:8] in 10-bit addressing mode.

R/W

Read/write bit.

When this bit = 1, a read sequence is requested.

When this bit = 0, a write sequence is requested.

Table 106. I2CxADR1 MMR in 10-Bit Address Mode

Bit

Name

Description

7:0

I2CLADR

These bits contain ADDR[7:0] in 10-bit addressing mode.

Table 107. I2CxDIV MMR

Bit

Name

Description

15:8

DIVH

These bits control the duration of the high period of SCLx.

7:0

DIVL

These bits control the duration of the low period of SCLx.

Rev. A | Page 63 of 96

ADuC7122BBCZ Datasheet(PDF) 63 Page - Analog Devices

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