ADuC7122BBCZ datasheet(73/96 Pages) AD

73 / 96 page

Data Sheet

ADuC7122

Rev. A | Page 73 of 96

PROGRAMMABLE LOGIC ARRAY (PLA)

The ADuC7122 integrates a fully programmable logic array

(PLA) that consists of two, independent but interconnected

PLA blocks. Each block consists of eight PLA elements, giving

each part a total of 16 PLA elements.

Each PLA element contains a two-input look-up table that can

be configured to generate any logic output function based on

two inputs and a flip-flop. This is represented in Figure 35.

LOOKUP

TABLE

Figure 35. PLA Element

In total, 32 GPIO pins are available on each ADuC7122 for the

PLA. These include 16 input pins and 16 output pins that need to

be configured in the GPxCON register as PLA pins before using

the PLA. Note that the comparator output is also included as

one of the 16 input pins.

The PLA is configured via a set of user MMRs. The output(s) of

the PLA can be routed to the internal interrupt system, to the

CONVSTE

signal of the ADC, to an MMR, or to any of the 16

PLA output pins.

The two blocks can be interconnected as follows:



Output of Element 15 (Block 1) can be fed back to Input 0 of

Mux 0 of Element 0 (Block 0)



Output of Element 7 (Block 0) can be fed back to the Input 0

of Mux 0 of Element 8 (Block 1)

Table 113. Element Input/Output

PLA Block 0

PLA Block 1

Element

Input

Output

Element

Input

Output

P2.7

P3.0

P1.4

P3.4

P2.2

P3.1

P1.5

P3.5

P0.6

P3.2

P0.5

P3.6

P0.7

P3.3

P0.4

P3.7

P0.1

P1.7

P2.1

P0.3

P0.0

P1.6

P2.0

P0.2

P1.1

P2.5

P2.3

P1.3

P1.0

P2.4

P2.6

P1.2

PLA MMRs Interface

The PLA peripheral interface consists of the 21 MMRs

described in Table 114 to Table 128.

Table 114. PLAELMx Registers

Name

Address

Default Value

Access

PLAELM0

0xFFFF0B00

0x0000

R/W

PLAELM1

0xFFFF0B04

0x0000

R/W

PLAELM2

0xFFFF0B08

0x0000

R/W

PLAELM3

0xFFFF0B0C

0x0000

R/W

PLAELM4

0xFFFF0B10

0x0000

R/W

PLAELM5

0xFFFF0B14

0x0000

R/W

PLAELM6

0xFFFF0B18

0x0000

R/W

PLAELM7

0xFFFF0B1C

0x0000

R/W

PLAELM8

0xFFFF0B20

0x0000

R/W

PLAELM9

0xFFFF0B24

0x0000

R/W

PLAELM10

0xFFFF0B28

0x0000

R/W

PLAELM11

0xFFFF0B2C

0x0000

R/W

PLAELM12

0xFFFF0B30

0x0000

R/W

PLAELM13

0xFFFF0B34

0x0000

R/W

PLAELM14

0xFFFF0B38

0x0000

R/W

PLAELM15

0xFFFF0B3C

0x0000

R/W

PLAELMx are Element 0 to Element 15 control registers. They

configure the input and output mux of each element, select the

function in the look-up table, and bypass/use the flip-flop. See

Table 115 and Table 118.

ADuC7122BBCZ Datasheet(PDF) 73 Page - Analog Devices

ADuC7122BBCZ Datasheet(HTML) 73 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL