M21050 datasheet(22/70 Pages) MA-COM

22 / 70 page

Mindspeed Technologies™

21050-DSH-001-F

Mindspeed Proprietary and Confidential

M21050 Data Sheet

1.1.16

Loss of Activity

By default, the LOA detector is enabled and can be disabled by setting CDR_ctrlA_N[1] = 0b, where N is mapped to

the CDR (number). Loss of activity measures the transition density of data to determine if the data is valid. During

small time intervals, variations are due to data content, packet headers, stress patterns, etc., which is taken into

account by averaging over a larger time period. In some applications, when data is not present, noise produces rail-

to-rail transitions that cause problems with level based detectors. These applications include cascaded CDRs,

high-gain crosspoints, as well as modules with optical amplifiers. As a result, the transition density LOA can sepa-

rate data from random noise, determine false lock at the wrong integer and non-integer data-rate, signal stuck high/

low conditions, and determine false lock to re-timed noise. Unlike level based detectors, it cannot determine false

lock onto low amplitude data, which is a condition that does not typically occur with backplane applications, and

can be handled by the limiting amplifier or pre-amplifier in modules. The LOA window is fixed at 25% to 100%.

1.1.17

Built-in Self Test (BIST) Overview

The M21050 contains a single BIST test pattern generator as well as a test pattern receiver. Both the BIST trans-

mitter (BIST Tx), and BIST receiver (BIST Rx) are designed to operate with fixed patterns. PRBS 27-1, 215-1, 223-

1, and 231-1 test patterns are provided. For 8b/10b testing, the fibre channel CRPAT and CJTPAT standard patterns

are supported. In addition, an 8b/10b countdown pattern is also provided; this is the 8b/10b representation of a

binary count from 255 to 0, while maintaining 8b/10b running disparity requirements. User programmable 16 bit

and 20 bit patterns are also provided; they are typically used to generate short patterns for debug, such as 1100b,

as well as 8b/10b idle or control characters. The BIST is designed to reduce system development time, as well as

product test costs, and can be used by both the equipment provider as well as the equipment end user.

When enabled, the BIST Rx allows one input from the CDR to enter the BIST receiver. The desired channel to

monitor is selected through a control register. The BIST Rx uses the recovered clock and data from the selected

CDR to drive the pattern checker. Every time a bit error is received, the error register is incremented. The maxi-

mum number of errors is FFh, and all subsequent errors will not be counted. At any time, the error register can be

cleared. By keeping track of the time between clear and read, a rough BER number can be obtained.

When enabled, the BIST Tx can broadcast the output test pattern to any of the CDR outputs (the BIST Tx and Rx

can be used at the same time). The BIST Tx contains an internal clock multiplier (PLL), that can take its input from

either the external reference frequency, or from the same CDR that is driving the BIST Rx (only in full rate mode,

DRD = 1).

Table 1-11.

LOL Window Size and Decision Time Examples

Condition

Nacq

Nnarrow

Nwide

Narrow

Window

(ppm)

Wide

Window

(ppm)

Decision

Time

(µs)

Hardwired mode

101b

0011b

±1465

±1955

420

Two-wire serial interface mode

101b

0011b

±1465

±1955

420

iFV = iFR

111b

0010b

±245

±975

1685

Fast lock

010b

0001b

±5860

±7800

Notes:

1. Decision time is calculated with iFR = 19.44 MHz; will scale proportionally with iFR range from 10 to 25 MHz.

2. Above are examples showing ability to tailor windows for data-rates, reference frequencies, and acquisition times.

M21050 Datasheet(PDF) 22 Page - M/A-COM Technology Solutions, Inc.

M21050 Datasheet(HTML) 22 Page - M/A-COM Technology Solutions, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL