Symbol

Pin

IO

Function

DIFF

VOH

15

O

Differential High Voltage Load

This output is connected to a load network which is ten times the

value of the load network connected to the differential PCLK pins

DIFF

VOL

16

O

Differentlal Low Voltage Load

This output is connected to a load network which is ten times the

value of the load network connected to the differential PCLK pins

DVDD

4

S

Digital VDD

This pin serves as the source for the internal CGS410 counter circuitry This input

should be well referenced to BVDD and bypassed to DGND

EN

28

I

An Active-High Level-Sensltlve TTL Compatible Input

This input is sampled on the falling edge

of CSB EN high allows data to be transferred to the shadow register in the write mode or to the shift

register in the read mode

EXTCLK

2

I

External Clock

When the internal multiplexer is set to EXTCLK mode the crystal and phase-locked

loop are bypassed and this TTL compatible input will drive the PCLK outputs and the L divider input

If the external VCO mode is invoked EXTCLK drives the P and N dividers When this input is not

selected it should be driven to a high or low to avoid oscillations

FILTER

12

O

Filter Output

This current source output is driven from the internal charge pump This output is left

floating in applications where only the internal low pass filters are used FILTER is used for

applications which require passive or active external LPF networks For passive LPF networks this

output should be connected directly to FREQCTL input and the LPF network (see

Figure 3-7 )

FREQCTL

11

I

Frequency Control

FREQCTL is the VCO voltage control input When in external loop filter mode

the voltage present on this input determines the VCO frequency For applications which require only

the internal filters this input is left unconnected This input is used for applications which require

external networks for loop filtering The input voltage range should not exceed AVDD and not go

below the AGND reference

LCLK

23

O

Load Clock Output

This CMOS compatible non-gated output is typically used in video applications

which require a programmable clock to produce lower output frequencies synchronous to PCLK

Typically this is used to clock video shift registers or RAMDACs

LCLK

EN

24

I

Load Clock Enable

This synchronous active high TTL compatible input selects whether the LCLK

output is disabled or enabled A HIGH level enables the LCLK output pin while a LOW disables

activity on the LCLK In the disabled state LCLK is driven high or low depending on the logic state of

the L counter when disabled Refer to the LCLK

EN timing specification

PCLK

18

O

DifferentIal PCLK Output

This high speed output is configured to drive a host of devices requiring

differential clock inputs Output voltage swing is defined by the differential level control bit (Bit 1)

PCLKB

19

O

Differential PCLK Output

This high speed output is configured to drive a host of devices requiring

differential clock inputs Output voltage swing is defined by the differential level control bit (Bit 1)

R

WB

27

I

ReadWrite Select

R

WB is a level sensitive TTL compatible input When writing values to the

chip the R

WB would be sampled low on the falling edge of CSB Conversely when reading values

the R

WB would be sampled high on the falling edge of CSB

XGND

8

S

Crystal Ground

This pin serves as the ground return for the internal oscillator circuitry All external

oscillator support be it active or passive should be tied to XGND for best performance

XTLIN

6

I

Crystal Input

XTLIN is designed to operate with crystal oscillator or ceramic resonator input For

crystal input applications the crystal should be the fundamental parallel mode type See the

applications diagrams for more information

XTLOUT

7

O

Crystal Output

This output is used as the Pierce Oscillator output for use with parallel mode

crystals An external resistor between XTLOUT and XTLIN will bias this stage to approximately

XVDD2 This output is left floating for applications which directly drive the XTLIN

XVDD

9

S

Crystal VDD

This positive power supply input sources the internal oscillator circuitry All external

oscillator support be it active or passive should be referenced to XVDD for best performance This

supply input must track DVDD to within 5%

4