The CGS410 allows the user to select the quantity of charge

pump current and its direction Specifying the direction of

charge flow is useful in situations where an external filter

andor VCO is incorporated See the applications section

for an example In situations where external networks lack

the charge sensitivity the amount of charge can be in-

creased at the user’s discretion

34 PROGRAMMABLE DIVIDER OPERATION

The CGS410 has four internal dividers (R N P and L)

which are programmed serially via the internal control regis-

ter

The R (reference) divider provides a reference frequency

from either a crystal or an externally generated clock

source The divisor range is contiguous and varies from 1 to

1023 The modulus selected is the direct binary equivalent

loaded in the serial control register at bit locations 24 – 33

The internal N divider provides a means of locking the VCO

with a constant tuning resolution that is independent of the

pixel system Its contiguous modulus range is 2 to 16383

The P (postscaling) divider provides a means of generating

an output over a wide frequency range from a VCO which

has a flxed frequency range The modulus selections of the

P divider range from 1 – 16 inclusive The modulus of this

divider is programmed with serial control register bits

16 – 19 The PCLK outputs are square when the P modulus

is 1 2 4 6 8 10 12 14 or 16 If the P modulus is 3 5 7 9

11 13 or 15 the PCLK outputs are low one less count than

it is high For example dividing by modulus 5 would result in

three counts high and two counts low

The L (load) divider provides a means of generating a load

clock by dividing the PCLK by a modulus ranging from 1 – 16

inclusive The modulus of the load divider is programmed

with serial control register bits 20 – 23 The L clock output is

derived from the output of the internal MUX so whichever

output is selected by the mux will be divided by L The L

clock can be asynchronously disabledenabled by a serial

bit The LCLK outputs are square when the L modulus is 1

2 4 6 8 10 12 14 or 16 If the L modulus is 3 5 7 9 11

13 or 15 the LCLK is high one less count than it is low For

example dividing by modulus 5 would result in three counts

low and two counts high

After setting the appropriate values of the registers the

CMOS PCLK output frequency can be calculated using the

formula below

R

P

35 CONTROL REGISTER OPERATION

The CGS410 serial control register consists of 47 bits each

of which control various internal functions as described later

in the section ‘‘Structure of the Internal Serial Control Regis-

ter’’ All bit locations are RAM based and are voIatile during

power cycling operations The CGS410 contains an internal

shadow register which directly reflects that of the serial shift

register The contents of the shadow register program the

CGS410 parameters The shadow register allows the user

to write a stream of data to the serial shift register then for

the last bit do a write followed by a transfer operation The

transferring operation allows all parameters to be loaded

into the respective target registers in a single clock cycle

This ensures that changes in clocking parameters take

place in a uniform manner

Read operations are performed in the opposite sequence

from that of write Here data is transferred from the shadow

register to the serial shift register on the first bit and serially

shifted out thereafter

Performing transfer operations is up to the discretion of the

system programmer In many instances the system may

only require partial diagnostic information from the internal

registers and hence avoid a full serial transfer This is easily

accomplished by transferring the data then shifting only

that portion required for the task The sequence can easily

be repeated without adverse affects on the shadow register

Bear in mind that the first data bit written will be the first bit

read-out

351 System Loading Sequence

All system access to the CGS410 takes place relative to the

rising or falling edge of CSB EN and R

WB must be stable

and in the desired state prior to the falling edge of CSB

while data must be present or sampled by the system CPU

during the rising edge of CSB

Serial write operations consist of setting both ENable and

R

WB low for the first N-1 bits Transfer of serial data to

the last bit-write bus cycle set EN high The CGS410 will

shift in the last bit then perform a transfer to the shadow

register Once the transfer takes place the PLL will immedi-

ately begin to lock to the new values

Serial read operations consist of setting ENable low and

R

WB high for all bits However if the programmer wishes

to refresh the data in the serial shift register a transfer oper-

ation is performed when reading the first bit On the first bit

read bus cycle set EN high The CGS410 will transfer all

data in the shadow resister to the shift register then shift out

the first valid data bit Note that the contents of the shadow

register are unchanged by the read transfer with no effect

on the CGS410 internal parameters or output clocks

The rest of the serial read operation consists of shifting data

bits 2 – 47 Each bit becomes valid at the DATA pin after

CSB goes low and then shifts on the positive edge of CSB

352 Structure of the Internal Serial Control Register

The following describes the bit structure of the Control Reg-

ister Where applicable all programmable registers values

are loaded with the LSB first

Serial Bit 1

Differential Level control This bit sets an internal bias level

to provide differential ‘‘large’’ (bit 1 high) or ‘‘small’’ (bit 0

low) signal swing On power-up this bit is low (small signal

swing)

6