CGS410 datasheet(10/18 Pages) NSC

10 / 18 page

30 Circuit Operation (Continued)

The values R1 C1 and C2 refer to the following filter config-

uration

TLF11919 – 9

FIGURE 3-7 External Low Pass Filter

The above equations refer to the low pass filter loop re-

sponse associated with a single phase comparator refer-

ence frequency In many situations the CGS410 will be re-

quired to generate many output frequencies Best perform-

ance is obtained by matching the filter to the required fre-

quency This may require different LPF component values

for each configuration In most instances selection of any of

the CGS410’s three internal filters will satisfy the LPF re-

quirements A fourth option allows the use of an external

configuration

When generating a wide range of output frequencies a

phase margin of approximately 60 degrees should be main-

tained for a theoretically stable system In practice wide

variation is possible Note that the equations expressed

above are functions of only N 0o Kp and Ko PCLK output

frequency is NOT included Since the CGS410 allows the

use of an external loop filter as well as three internal filters

there should always exist a configuration of counter values

that will produce a quality clock output without the need to

externally switch loop filter values

37 CLOCK DEGLITCHING CONSIDERATIONS

The CGS410’s automatic deglitching function ensures that

the clock output pulse width will be no shorter than the brief-

est clock high or low time currently programmed Deglitch-

ing the clock outputs allows the system to maintain proper

state throughout the clock change cycle

When the user loads the shadow register with a code that

changes the state of serial bits 14 through 19 (the P counter

modulus or the internal clock MUX select) the deglitching

process is automatically initiated The PCLK outputs are

temporarily frozen and then are restarted several PCLK pe-

riods later synchronous to the new output frequency

38 CONFIGURABLE DIFFERENTIAL OUTPUT BUFFERS

For proper operation a 101 resistive relationship will exist

between the DIFF

VOHVOL pin loads and the PCLK dif-

ferential loads Adhering to this relationship will provide the

correct voltage drive at the PCLK differential outputs

39 TERMINATION CONSIDERATIONS

Each differential PCLK output serves as a current source to

a resistive termination network The termination network

matches the characteristic impedance as seen by the PCLK

system trace Proper network component selection also bi-

ases the differential output stage to maintain the proper

VOH and VOL values The most common network uses a

resistive pull-uppull-down combination (see

Figure 3-9 )

The combination of the resistive devices provides a DC

Thevenin equivalent with a specified voltage output and

load resistance

TLF11919 – 10

FIGURE 3-8 Termimation

Figure 3-8 illustrates the electrical model for driving the dif-

ferential PCLK outputs down a transmission line It termi-

nates in a Thevenin equivalent consisting of a resistance

(RL) and a source voltage (VL) Modulating the output driver

gate modulates the output PMOS source current (IO) The

combination of source current and load resistance results in

an output voltage For properly terminated systems the

characteristic impedance of the signal line (ZL) should

closely approximate the effective RL When using a Theve-

nin equivalent circuit (see

Figure 3-8 ) the effective RL is

described as the open circuit voltage divided by the short

circuit current

RL e VOC ISC e (R1 R2)(R1 a R2)

In addition to maintaining the proper resistance the resis-

tors must be selected to provide the proper VL for the cir-

cuit The resistors should be selected such that VOL can be

reached VOL is the most important parameter The follow-

ing rule will apply

VL k VOL where typically VL e is 150 mV–500 mV

below the VOL

VL is calculated as the open circuit voltage

VL e VOC e BVDD R2 (R1 a R2)

In all the equations the output PMOS source current (IO)

should never exceed 21 mA

TLF11919 – 11

FIGURE 3-9 Pull-UpPull-Down DC Termination

Figure 3-10 illustrates a typical termination that will assume

the VOH and VOL requirements are met without overdriving

the CGS410 outputs The value of VOL must meet the re-

quirements of the destination device For positive ECL logic

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