CGS410 datasheet(9/18 Pages) NSC

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30 Circuit Operation (Continued)

Note that with VCO

PST high the charge pump output

voltage is clamped to AGND This condition will prevent the

PLL from locking

Proper VCO lock operation will require the

user to reset this bit

36 LOOP FILTER CHARACTERISTICS

The function of the low pass filter (LPF) is to transform the

CPO charge output into a DC voltage seen on the VCO

input A variety of LPF configurations exist This particular

architecture is suited towards a CRC type of configuration

Figure 3-7 shows such an architecture The desired Bode

plot of gain and phase is shown in

Figure 3-6 with 20 dB

decade slope at 0o for stability at unity gain

Capacitor C2 governs the PLL’s ability to reject instanta-

neous bit jitter This represents the high frequency pole R1

and C1 determine the low frequency zero When R1 C1 and

C2 values are properly calculated 0o will fall in the

20 dBdecade flattened response and will help track out

the 1f noise inherent in the VCO An added benefit is that

the LPF phase response is symmetrical at this frequency

Increasing or decreasing C2 will move the high frequency

pole up or down likewise with the R1 and C1 combination

Converging and expanding the pole pairs will result in a un-

derdamped or overdamped filter Resistive component R1

directiy affects this response

Loop filter components can vary somewhat to conform to

the given application requirements Underdamping the loop

response causes decreased loop stability (ultimately result-

ing in loop oscillation) but will decrease lock time an ad-

vantage in applications where lock time is critical On the

other hand overdamping the filter response leads to de-

creased phase noise while increasing the loop lock time

Generally setting C2 at 110th to 150th the value of C1 will

provide reasonable loop response

Selecting the appropriate loop filter depends on the fre-

quency at the phase comparator The most effective filter-

ing ranges for the three internal filters are

Loop Filter 1 03 MHz – 10 MHz (80 k N k 500)

Loop Filter 2 10 MHz – 30 MHz (30 k N k 80)

Loop Fllter 3 30 MHz – 60 MHz (15 k N k 30)

Best performance (lowest phase noise) is obtained by pro-

gramming FREF to fall somewhere in the middle of any of

these frequency ranges

361 Loop Filter Calculations

Several constraints need to be known in order to determine

the external loop filter components for external loop filter

operation the loop divide ratio (N) the phase comparator

gain (Kp) the VCO gain (Ko) the loop bandwidth (0o) and

the phase margin (F)

The constants for the CGS410 are as follows

Ko e 500E6 radv

Kp e 4 mArad when CPO SEL (bit 8) e 0

12 mArad when CPO SEL (bit 8) e 1

The variable parameters for the CGS410 are as follows

N e N counter modulus

R e R counter modulus

fXTAL e frequency at XTLlN pin (in Hz)

N is equal to the VCO frequency divided by the frequency

input at FREF The loop bandwidth (0o) is recommended to

be about 130th of the FREF frequency (times 2q radians)

Most users will find the following set of equations give good

loop filter values for frequency synthesis applications

R1 e (023 N fXTAL)(Kp Ko R)

C1 e (684 Kp Ko R2)(N fXTAL2)

C2 e C1 20

The following equations can be used for different cutoff fre-

quencies and phase margins

For F e 57 degrees phase margin

R1 e (11 N 0o)(Kp Ko)

C1 e (3 Kp Ko)(N 0o2)

C2 e (015 Kp Ko)(N 0o2) (120th C1 value)

For a phase margin other than 57 degrees

R1 e (Cosec F a 1) (N 0o)(2 Kp Ko)

C1 e (Tan F) (2 Kp Ko)(N 0o2)

C2 e (Sec F b Tan F) (Kp Ko)(N 0o2)

TLF11919 – 8

FIGURE 3-6 Bode Plot of Loop Filter Response

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