CGS410 datasheet(11/18 Pages) NSC

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30 Circuit Operation (Continued)

the resistive termination is normally set to provide a voltage

of 3V This is readily accomplished with R1 e 220 and

R2 e 330 With the control register differential level (bit 1)

equal to 0 the output VOL e BVDD

0642V or 321V at

BVDD e 5V The VOH is typically BVDD

0824V or 412V

at BVDD e 5V In this example

IO(MAX) e (VOH b VL)RL

(412 b 3)132

95 mA

Generation of VOH requires the maximum IO Since the

CGS410 can provide up to 21 mA of output source for VOH

this is well within driving specifications

TLF11919 – 12

FIGURE 3-10 Typical Termination (Bit 1 e 0)

Other factors which influence the differential output re-

sponse include the characteristic impedance of the line (ZL)

and capacitive loads The characteristic impedance of the

‘‘stripline’’ connecting the CGS410 output to the destination

device input should match the Thevenin equivalent of the

line termination to assure maximum power transfer glitch-

free clock outputs and reduced EMI

Capacitive loading will affect the rise and fall times of the

output waveform The current required is i C VT

Figure 3-11 indicates typical loading parameters used for

driving differential output capacitive loads for frequencies

from 25 MHz to 200 MHz with a 1V differential voltage

swing In addition the resulting graph bases the voltage

slew rate (vt) for 110 of the operating frequency period

The graph illustrates the fact that as the output frequency

and capacitance increase the amount of source current

must also increase to maintain reasonable slew rates

TLF11919 – 13

FIGURE 3-11 PCLKPCLKB Load vs Frequency

CMOS

PCLK drive requirements vary greatly from those of

the PCLK differential counterparts because the output buff-

er size and the output impedance are higher Best perform-

ance is usually obtained by placing a series resistor on the

output and then driving to the receiving device Selection of

the resistor is best obtained on an empirical basis Normally

resistor sizes starting in the 10X –80X range provide a good

start

Figure 3-10 shows a typical termination scheme for

60 – 70 board impedance

310 SYSTEM INTERFACE CONSIDERATIONS

The CGS410 data bus can be managed by a wide variety of

controllers If a serial data source is not available from the

controller external serializing circuitry or slight bus modifi-

cation may be required

Figure 3-12 illustrates a generic hardware system imple-

mentation where the CGS410 control signals are qualified

through a memory map In this example the CGS410 is

mapped into two address locations This particular mapping

scheme allows

1) typical readwrite operations to execute through one

mapped port

2) transfer operations to execute through the second

mapped port (see Figure 3-12)

Depending on the system configuration CGS410 control

signals such as R

WB may be connected directiy to a qual-

ified CPU strobe RWE In this example the system bus

data line zero D 0 serves as the DATA port of the CGS410

The control signal EN may be derived from address decode

select logic and can maintain any state during non-CGS410

accesses

The control signal CSB requires the greatest attention be-

cause it is the CGS410’s clocking agent Care must be tak-

en to ensure that no activity takes place on this input during

non-CGS410 accesses

Note that when this input is

strobed all control and data present at the CGS410 must

conform to the respective rising and falling edges of this

signal as specified in the timing diagrams in this data sheet

CSB may be generated from a variety of system sources A

qualified CPU WAIT may serve as one source Other timing

requirements may need a timing generator (such as a two-

state machine) to generate CSB

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