CGS410 datasheet(5/18 Pages) NSC

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30 Circuit Operation

The CGS410 programmable clock generator uses a crystal

oscillator as a frequency reference to generate clock sig-

nals for video applications such as display systems or disk

drive constant density recording The reference may come

from any source as long as input specifications are main-

tained Both single-ended (CMOS) and differential clock

outputs are generated Both clock outputs are synchronized

to simplify system timing A unique combination of internal

functions (such as the VCO the crystal oscillator a phase

comparator various programmable counters and a read-

able 47-bit serial control register) allows for versatility and

ease of design

31 INTERNAL VCO OPERATION

No external VCO inductor or capacitor components are re-

quired for operation simplifying PC board layout require-

ments P counter programmability is contiguous from 1 to

16 although a 50% duty cycle will be created only if the P

modulus is an even number or if the P modulus is 1

311 VCO Tuning Characteristics

The CGS410 VCO requires an input voltage to set the prop-

er operating frequency The input voltage is the direct result

of charge sourced or sinked off the LPF network The func-

tion of the LPF is to convert the charge to voltage (see

‘‘Loop Filter Characteristics’’) The VCO requires the input

voltage to be set in the linear portion of the input range The

VCO output frequency is a function of the VCO gain (FVCO)

and the range of the input voltage

Normal or linear VCO operation will place the input voltage

range from AVDD3 (the lowest frequency response) to ap-

proximately AVDD b 15V (the highest frequency re-

sponse) The linear operating range is illustrated in

Figure

3-1 with VCO output frequency (FVCO) expressed as a volt-

age filter input (VFILTER)

TLF11919 – 3

FIGURE 3-1 Linear Operating Range

Applying an input voltage beyond the intended range will

force the VCO to rail high or low Input voltages which ex-

ceed AVDD or go negative with respect to AGND can dam-

age the CGS410

32 CRYSTAL OSCILLATOR OPERATION

The XTLIN and XTLOUT pins are used in conjunction with

an external crystal two capacitors and two resistors to form

an external oscillator tank circuit The crystal should be a

fundamental parallel mode type XTLOUT serves as the

driving source to the crystal Consideration should be given

to avoiding crystal overdrive situations XTLOUT should

show an output waveform well within the XVDD and XGND

boundary conditions The elements forming the crystal tank

should be low-leakage devices Capacitor values (per crys-

tal leg) will typically fall within the range of 10 pF – 40 pF

The crystal oscillator divide-by-2 output may be directed to

appear at the clock outputs depending on the state of the 3

to 1 MUX On power up both differential and CMOS

PCLK

outputs will reflect half the oscillator frequency input The

XTLIN pin can be driven from a variety of sources including

ECL TTL or CMOS logic Attach a coupling capacitor into

the XTLIN pin when using a TTL or small-signal source

(such as ECL) Please see application diagrams for details

The CGS410 may be used to genlock to an external clock

source

33 PHASE COMPARATOR OPERATION

The phase comparator compares the difference in clock

edges between the internal N and R counter outputs The

difference results as either a charge source (pump-up) or

charge sink (pump-down) The amount of charge is directly

proportional to the phase difference (see

Figure 3-2 ) The

phase comparator controls the VCO by comparing the

phase of a derived signal from a known accurate reference

source such as a crystal or an external reference signal In

genlocking situations the reference source may be a con-

stant stream of pulses such as an external HSYNC

TLF11919 – 4

FIGURE 3-2 Phase ComparatorCharge Pump

The VCO-derived signal is divided by N and applied to one

phase comparator input The R divider output serves as the

other phase comparator reference input The comparator

functions as a three-state machine providing a pump-up

state when R leads N and a pump-down state when N

leads R This situation exists only when there is a difference

between the two input edges The VCO frequency is then

increased or decreased in the closed loop system At all

other times the phase comparator is in a tri-state condition

The direction and amount of charge on the FILTER pin is

proportional to the difference in the phase comparator input

edges The charge flow is made up of correction pulses

The resulting correction pulses are converted to a voltage

as dictated by the LPF network Selection of LPF compo-

nents characterizes the resulting voltage and phase re-

sponse

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