CGS410 datasheet(12/18 Pages) NSC

12 / 18 page

30 Circuit Operation (Continued)

TLF11919 – 14

FIGURE 3-12 Serial Interface Example

TLF11919 – 15

FIGURE 3-13 Minimum Cost k80 MHz CGS410 Implementation

311 APPLlCATlONS

Many applications exist which can use the synthesized

clock capability of the CGS410 Because of the CMOS na-

ture of the device it can maintain high frequency clock rates

while consuming little current

This allows use of the

CGS410 in battery powered systems

Application requirements for the CGS410 are largely dictat-

ed by the user

Figure 3-13 illustrates a low cost implemen-

tation Pulling the PCLK outputs to BVDD will turn the out-

puts off In this configuration DIFF

VOH and DIFF

VOL

are also tied to BVDD CMOS

PCLK serves as the fre-

quency output source Note also that all LCLK EXTCLK

FILTER and crystal functions can be modified to address

the needs of the application

Figure 3-14 shows the common clock drive requirements for

a video-based system The CGS410 provides all clocking

sources LCLK provides a synchronized low-frequency sub-

multiple of PCLK for driving the RAMDAC load data require-

ments In addition LCLK can easily be used to drive the

respective frame buffer array which clocks the display data

The Load Clock Enable (LCLK

EN) can be used to disable

load clock pulses during screen blanking intervals

CGS410 Datasheet(PDF) 12 Page - National Semiconductor (TI)