COP685BC datasheet(38/57 Pages) NSC

38 / 57 page

Comparators (Continued)

CMP1EN

Enables comparator 1 (“1”=enable). If compara-

tor 1 is disabled the associated L-pins can be

used as standard I/O.

Reserved This bit is reserved and should be zero.

The Comparator Select/Control bits are cleared on RESET

(the comparator is disabled). To save power, the program

should also disable the comparator before the device enters

the HALT mode.

The Comparator rise and fall times are symmetrical. The

user program must set up the Configuration and Data regis-

ters of the L port correctly for comparator Inputs/Output.

Interrupts

INTRODUCTION

Each device supports eleven vectored interrupts. Interrupt

sources include Timer 0, Timer 1, Port L Wakeup, Software

Trap, MICROWIRE/PLUS, and External Input.

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

The Software trap has the highest priority while the default

VIS has the lowest priority.

Each of the 11 maskable inputs has a fixed arbitration rank-

ing and vector.

Figure 35 shows the Interrupt Block Diagram.

DS012067-36

The BOXED area shows logic from PWM Timer. Comparator 2 output (CMP2OE) must be disabled in order to use PWM0 output.

FIGURE 34. Comparator Block

COP685BC Datasheet(PDF) 38 Page - National Semiconductor (TI)