COP685BC datasheet(41/57 Pages) NSC

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Interrupts (Continued)

TABLE 9. Interrupt Vector Table

Arbitration

Source

Vector Address

Ranking

Hi-Low Byte

Software Trap

0yFE–0yFF

Reserved

0yFC–0yFD

CAN Receive

0yFA–0yFB

CAN Error

0yF8–0yF9

(transmit/receive)

CAN Transmit

0yF6–0yF7

Pin G0 Edge

0yF4–0yF5

IDLE Timer Underflow

0yF2–0yF3

Timer T1A/Underflow

0yF0–0yF1

Timer T1B

0yEE–0yEF

MlCROWIRE/PLUS

0yEC–0yED

PWM timer

0YEA–0yEB

Reserved

0yE8–0yE9

Reserved

0yE6–0yE7

Reserved

0yE4–0yE5

Port L/Wake Up

0yE2–0yE3

Default VIS Interrupt

0yE0–0yE1

Note 18: y is VIS page, y

≠ 0

If, by accident, a VIS gets executed and no interrupt is ac-

tive, then the PC (Program Counter) will branch to a vector

located at 0yE0-0yE1.

VIS Execution

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc...) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If the only active inter-

rupt is software trap, than E0 is generated. This number re-

places the lower byte of the PC. The upper byte of the PC re-

mains unchanged. The new PC is therefore pointing to the

vector of the active interrupt with the highest arbitration rank-

ing. This vector is read from program memory and placed

into the PC which is now pointed to the 1st instruction of the

service routine of the active interrupt with the highest arbitra-

tion ranking.

Figure 36 illustrates the different steps performed by the VIS

instruction.

Figure 37 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

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