COP685BC datasheet(18/57 Pages) NSC

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Timers (Continued)

a fixed, non-programmable repetition rate of 255 PWM clock

cycles. The timer is clocked by the output of an 8-bit, pro-

grammable prescaler, which is clocked with the chip’s CKI

frequency. Thus the PWM signal frequency can be calcu-

lated with the formula:

Selecting the PWM mode by setting PWMD to “1”, but not

yet starting the timer (PWON is “0”), will set the timer output

to “1”.

The contents of an 8-bit register, RLON, multiplied by the

clock cycle of the prescaler output defines the time between

overflow (or starting) and the falling edge of the PWM output.

Once the timer is started, the timer output goes low after

RLON cycles and high after a total of 255 cycles. The proce-

dure is continually repeated. In PWM mode the timer is avail-

able at pins PWM0 and/or PWM1, provided the port configu-

ration bits for those pins are defined as outputs and the

PWEN0 and/or PWEN1 bits in the PWMCON register are

set.

The PWM timer is started by the software setting the PWON

bit to “1”. Starting the timer initializes the timer register. From

this point, the timer will continually generate the PWM signal,

independent of any processor activity, until the timer is

stopped by software setting the PWON bit to “0”. The pro-

cessor is able to modify the RLON register regardless of

whether the timer is running. If RLON is changed while the

timer is running, the previous value of RLON is used for com-

parison until the next overflow occurs, when the new value of

RLON is latched into the comparator inputs.

When the timer overflows, the PWM pending flag (PWPND)

is set to “1”. If the PWM interrupt enable bit (PWIE) is also

set to “1”, timer overflow will generate an interrupt. The

PWPND bit remains set until the user’s software writes a “0”

to it. If the software writes a “1” to the PWPND bit, this has no

effect. If the software writes a “0” to the PWPND bit at the

same time as the hardware writes to the bit, the hardware

has precedence.

Note: The software controlling the duty cycle is able to change the PWM duty

cycle without having to wait for the timer overflow.

Figure 14 shows how the PWM output is implemented. The

PWM Timer output is set to “1” on an overflow of the timer

and set to “0” when the timer is greater than RLON. The out-

put can be multiplexed to two pins.

Capture Mode

If the PWM mode bit (PWMD) is set to “0” the PWM Timer

operates in capture mode. Capture mode allows the pro-

grammer to test whether the frequency of an external source

exceeds a certain threshold.

If PWMD is “0” and PWON is “0”, the timer output is set to

“0”. In capture mode the timer output is available at pin

PWM1, provided the port configuration register bit for that

pin is set up as an output and the PWEN1 bit in the

PWMCON register is set. Setting PWON to “1” will initialize

the timer register and start the counter. A rising edge, or if se-

lected, a falling edge, on the FMONIN input pin will initialize

the timer register and clear the timer output. The counter

continues to count up after being initialized. The ESEL bit de-

termines whether the active edge is a rising or a falling edge.

If, in capture mode PWM0 is configured incorrectly as an

output and is enabled via the PWEN0 bit, the timer output

will feedback into the PWM block as the timer input.

The contents of the counter are continually compared with

the RLON register. If the frequency of the input edges is suf-

ficiently high, the contents of the counter will always be less

than the value in RLON. However, if the frequency of the in-

put edges is too low, the free-running counter value will

count up beyond the value in RLON.

When the counter is greater than RLON, the PWM timer out-

put is set to “1”. It is set to “0” by a detected edge on the timer

input or when the counter overflows. When the counter be-

DS012067-14

FIGURE 14. PWM Mode Operation

COP685BC Datasheet(PDF) 18 Page - National Semiconductor (TI)

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