COP685BC datasheet(47/57 Pages) NSC

47 / 57 page

Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

Contents

00 to 2F

On-Chip RAM bytes (48 bytes)

30 to 7F

Unused RAM Address Space (Reads As All

Ones)

80 to 9F

Unused RAM Address Space (Reads

Undefined Data)

PSCAL, PWM timer Prescaler Register

RLON, PWM timer On-Time Register

PWMCON, PWM Control Register

A3 to AF

Reserved

TXD1, Transmit 1 Data

TXD2, Transmit 2 Data

TDLC, Transmit Data Length Code and

Identifier Low

TID, Transmit Identifier High

RXD1, Receive Data 1

RXD2, Receive Data 2

RIDL, Receive Data Length Code

RID, Receive Identify High

CSCAL, CAN Prescaler

CTIM, Bus Timing Register

CBUS, Bus Control Register

TCNTL, Transmit/Receive Control Register

RTSTAT Receive/Transmit Status Register

TEC, Transmit Error Count Register

REC, Receive Error Count Register

Reserved

C0 to C7

Reserved

WKEDG, MIWU Edge Select Register

WKEN, MIWU Enable Register

WKPND, MIWU Pending Register

CB to CF

Reserved

PORTLD, Port L Data Register

PORTLC, Port L Configuration Register

PORTLP, Port L Input Pins (Read Only)

CMPSL, Comparator control register

PORTGD, Port G Data Register

PORTGC, Port G Configuration Register

PORTGP, Port G Input Pins (Read Only)

D7 to DB

Reserved

PORTD, Port D output register

DD to DF

Reserved for Port D

E0 to E5

Reserved

T1RBLO, Timer T1 Autoload Register Lower

Byte

T1RBHI, Timer T1 Autoload Register Upper

Byte

ICNTRL, Interrupt Control Register

SIOR, MICROWIRE/PLUS Shift Register

Address

Contents

TMR1LO, Timer T1 Lower Byte

TMR1HI, Timer T1 Upper Byte

T1RALO, Timer T1 Autoload Register Lower

Byte

T1RAHI, Timer T1 Autoload Register T1RA

Upper Byte

CNTRL, Control Register

PSW, Processor Status Word Register

F0 to FB

On-Chip RAM Mapped as Registers

X Register

SP Register

B Register

Reserved (Note 20)

Note 19: Reading memory locations 30–7F Hex will return all ones. Reading

other unused memory locations will return undefined data.

Note 20: In devices with more than 128 bytes of RAM, location 0FF is used

as the Segment register to switch between different Segments of RAM

memory. In this device location 0FF can be used as a general purpose, on-

chip RAM mapped register. However, the user is advised that caution should

be taken in porting software utilizing this memory location to a chip with more

than 128 bytes of RAM.

Addressing Modes

There are ten addressing modes, six for operand addressing

and four for transfer of control.

OPERAND ADDRESSING MODES

This is the “normal” addressing mode. The operand is the

data memory addressed by the B pointer or X pointer.

decrement of pointer)

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

pointer or X pointer. This is a register indirect mode that au-

tomatically post increments or decrements the B or X regis-

ter after executing the instruction.

Direct

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

Immediate

The instruction contains an 8-bit immediate field as the oper-

and.

Short Immediate

This addressing mode is used with the Load B Immediate in-

struction. The instruction contains a 4-bit immediate field as

the operand.

Indirect

This addressing mode is used with the LAID instruction. The

contents of the accumuiator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

COP685BC Datasheet(PDF) 47 Page - National Semiconductor (TI)

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