COP685BC datasheet(12/57 Pages) NSC

12 / 57 page

Functional Description (Continued)

The device has 64 bytes of RAM. Sixteen bytes of RAM are

mapped as “registers” at addresses 0F0 to 0FF Hex. These

registers can be loaded immediately, and also decremented

and tested with the DRSZ (decrement register and skip if

zero) instruction. The memory pointer registers X, SP, and B

are memory mapped into this space at address locations

0FC to 0FE Hex respectively, with the other registers (other

than reserved register 0FF) being available for general us-

age.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

RESET

The RESET input when pulled low initializes the microcon-

troller. lnitialization will occur whenever the RESET input is

pulled low. Upon initialization, the data and configuration

registers for Ports L and G, are cleared, resulting in these

Ports being initialized to the TRI-STATE mode. Port D is ini-

tialized high with RESET. The PC, PSW, CNTRL, and ICN-

TRL control registers are cleared. The Multi-Input Wake Up

registers WKEN, WKEDG, and WKPND are cleared. The

Stack Pointer, SP, is initialized to 02F Hex.

The following initializations occur with RESET:

Port L: TRI-STATE

Port G: TRI-STATE

Port D: HIGH

PC: CLEARED

PSW, CNTRL and ICNTRL registers: CLEARED

Accumulator and Timer 1:

RANDOM after RESET with power already applied

RANDOM after RESET at power-on

SP (Stack Pointer): Loaded with 2F Hex

CMPSL (Comparator control register): CLEARED

PWMCON (PWM control register): CLEARED

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-up

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-up

CAN:

The CAN Interface comes out of external reset in the

“error-active” state and waits until the user’s software

sets either one or both of the TXEN0, TXEN1 bits to “1”.

After that, the device will not start transmission or recep-

tion of a frame until eleven consecutive “recessive” (un-

driven) bits have been received. This is done to ensure

that the output drivers are not enabled during an active

message on the bus.

CSCAL, CTlM, TCNTL, TEC, REC: CLEARED

RTSTAT: CLEARED with the exception of the TBE bit

which is set to 1

RID, RIDL, TID, TDLC: RANDOM

ON-CHIP POWER-ON RESET

The device is designed with an on-chip power-on reset cir-

cuit which will trigger a 256 t

c delay as VCC rises above the

minimum RAM retention voltage (V

r). This delay allows the

oscillator to stabilize before the device exits the reset state.

The contents of data registers and RAM are unknown follow-

ing an on-chip power-on reset. The external reset takes pri-

ority over the on-chip reset and will deactivate the 256 t

c de-

lay if in progress.

When using external reset, the external RC network shown

Figure 6 should be used to ensure that the RESET pin is

held low until the power supply to the chip stabilizes.

Under no circumstances should the RESET pin be allowed

to float. If the on-chip power-on reset feature is being used,

RESET should be connected directly to V

CC. Be aware of

the Power Supply Rise Time requirements specified in the

DC Specifications Table. These requirements must be met

for the on-chip power-on reset to function properly.

The on-chip power-on reset circuit may reset the device if

the operating voltage (V

CC) goes below Vr.

Oscillator Circuits

The chip can be driven by a clock input on the CKI input pin

which can be between DC and 10 MHz. The CKO output

clock is on pin G7. The CKI input frequency is divided by 10

to produce the instruction cycle clock (1/t

c).

Figure 7 shows the Crystal diagram.

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop crys-

tal (or resonator) controlled oscillator.

Table 1 shows the component values required for various

standard crystal values.

DS012067-6

RC > 5 x Power Supply Rise Time

FIGURE 6. Recommended Reset Circuit

DS012067-7

FIGURE 7. Crystal Oscillator Diagram

COP685BC Datasheet(PDF) 12 Page - National Semiconductor (TI)

COP685BC Datasheet(HTML) 12 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL