ADC12L080 datasheet(21/31 Pages) TI1

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ADC12L080

www.ti.com

SNAS200B – OCTOBER 2004 – REVISED MARCH 2013

The OF pin is used to determine the digital data output format. When this pin is high, the output formant is two's

complement. When this pin is low the output format is offset binary. Changing this pin while the device is

operating will result in uncertainty of the data for a few conversion cycles.

The PD pin, when high, holds the ADC12L080 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 50 mW and is not affected by the clock frequency, or by

whether there is a clock signal present. The output data pins are undefined and the data in the pipeline is

corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 30, 31 and 32.

These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before

conversions can be accurate. See Reference Pins.

OUTPUTS

The ADC12L080 has 12 TTL/CMOS compatible Data Output pins. The output data is present at these outputs

while the PD pin is low. While the tOD time provides information about output timing, a simple way to capture a

valid output is to latch the data on the rising edge of the conversion clock (pin 10).

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging

current spikes can cause on-chip noise and couple into the analog circuitry, degrading dynamic performance.

Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this

problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase, making it

difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers between the ADC outputs and any other circuitry (74ACQ541, for example). Only one driven

input should be connected to each output pin. Additionally, inserting series 100

Ω resistors at the digital outputs,

close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output

currents, which could otherwise result in performance degradation. See Figure 38.

While the ADC12L080 will operate with VDR voltages down to 1.8V, tOD increases with reduced VDR. Be careful of

external timing when using reduced VDR.

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