ADC12L080 datasheet(9/31 Pages) TI1

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ADC12L080

www.ti.com

SNAS200B – OCTOBER 2004 – REVISED MARCH 2013

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =

+2.5V, PD = 0V, VREF = +1.0V external, VCM = 1.65V, RS < 100Ω, fCLK = 80 MHz, tr = tf = 2 ns, fIN = 70 MHz, CL = 15 pF/pin.

Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1) (2) (3) (4) (5) (6)

Units

Symbol

Parameter

Conditions

Typical(4)

Limits(4)

(Limits)

Maximum Clock Frequency

MHz (min)

Minimum Clock Frequency

MHz

% (max)

Clock Duty Cycle

% (min)

tCH

Clock High Time

5.5

ns (min)

tCL

Clock Low Time

5.5

ns (min)

tCONV

Conversion Latency

Clock Cycles

VDR = 2.5V

5.2

8.3

ns (max)

tOD

Data Output Delay after Rising CLK Edge

VDR = 3.3V

4.8

7.5

ns (max)

tAD

Aperture Delay

tAJ

Aperture Jitter

0.7

ps rms

0.1 µF on pins 30, 31, 32,

tPD

Power Down Mode Exit Cycle

µs

and 1.0 µF from pin 30 to 31

(1)

The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited

per(6). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example,

if VA is 3.3V, the full-scale input voltage must be ≤3.4V to ensure accurate conversions.

(2)

To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +1.0V (2 VP-P differential input), the 12-bit LSB is 488 µV.

(4)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to TI's AOQL (Average

Outgoing Quality Level).

(5)

Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.

(6)

When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA, VD or VDR), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the

power supplies with an input current of 25 mA to two.

Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC.

CONVERSION LATENCY See PIPELINE DELAY.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the ADC clock input signal.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

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