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LAYOUT

ADS8422

SLAS512B – JUNE 2006 – REVISED DECEMBER 2006

ADC powerdown is activated by asserting PD1 to 0 for longer than 1.5

µs. If the signal PD1 is asserted 0 for

less than 0.5

µs, the ADC is only reset and any ongoing conversion aborted. See Figure 26. ADC operation can

be resumed from ADC powerdown by de-asserting the PD1 pin. In ADC power-down mode, the analog outputs

from the ADC(COMMOUT, REFOUT) are not powered down thereby reducing the power-on time.

Full chip power-down is activated by turning off the power supply or by asserting both, PD1 = 0 and PD2 = 0 for

longer than 1.5

µs (see Figure 27). In this mode, even the analog outputs of the ADC (COMMOUT, REFOUT)

are powered down thereby giving maximum power saving. Device operation can be resumed from full chip

power-down by turning on the power supply or by deasserting both, PD1 = 1 and PD2 = 1.

Table 3. Effects of RESET, PD1, and PD2

COMMAND

APPLICATION TIME

POWER WHEN APPLIED

RESUME TIME

RESET/PD1 = 0

20 ns

No change

20 ns

PD1 = 0, PD2 = 1

1.5

µs

17mW

5

µs

PD1 = PD2 = 0

1.5

µs

40

µW

25 ms

PD1 = 1, PD2 = 0

Reserved – Do not use this combination

For optimum performance, care should be taken with the physical layout of the ADS8422 circuitry.

As the ADS8422 offers single-supply operation, it is often used in close proximity with digital logic,

microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and

the higher the switching speed, the more difficult it is to achieve good performance from the converter.

The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground

connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving

any single conversion for an n-clock SAR converter, there are n windows in which large external transient

voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby

digital logic, or high power devices. The 50 ns period before BUSY falls should be kept free of supply glitches.

The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the

external event.

On average, the ADS8422 draws very little current from an external reference as the reference voltage is

internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive

the bypass capacitor or capacitors without oscillation. A 0.1-

µF bypass capacitor is recommended from pin 1

directly to REFM (pin 48). REFM and AGND should be shorted on the same ground plane underneath the

device.

The AGND, BDGND, and AGND pins should be connected to a clean ground point. In all cases, this should be

the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital

signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The

ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.

As with the AGND connections, +VA and +VAREG should be connected to their respective power supply planes

or traces that are separate from the connection for digital logic, until they are connected at the power entry point.

Power to the ADS8422 should be clean and well bypassed. A 0.1-

µF ceramic bypass capacitor should be placed

as close to the device as possible. See Table 4 for capacitor placement. In addition, a 1-

µF to 10-µF capacitor is

recommended. In some situations, additional bypassing may be required, such as a 100-

µF electrolytic capacitor

or even a Pi filter made up of inductors and capacitors — all designed to essentially low-pass filter the +5-V

supply, thus removing the high frequency noise.

Table 4. Power Supply Decoupling Capacitor Placement

POWER SUPPLY PLANE

CONVERTER

CONVERTER ANALOG SIDE

DIGITAL SIDE

SUPPLY PINS

Pin pairs that require shortest path to decoupling capacitors

(4,5), (9,8), (10,12), (13,15), (43,44), (46,45)

(24,25), (34,35)

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