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TIMING CHARACTERISTICS FROM DIGITAL INPUTS

TIMING CHARACTERISTICS OF DIGITAL OUTPUTS

ADS8422

SLAS512B – JUNE 2006 – REVISED DECEMBER 2006

All specifications typical at –40

PARAMETER

MIN

TYP

MAX

UNIT

CONVERSION AND ACQUISITION

Acquisition time, internal to device, not externally visible

70

ns

Pulse duration, CONVST low

20

ns

Pulse duration, CONVST high

100

ns

Period, CONVST

250

ns

30

ns

10

ns

POWER DOWN

PD1 low for only ADC reset (no powerdown)

20

500

Pulse duration

PD1 low for ADC reset and also ADC powerdown

1500

ns

PD2 low pulse duration for REFOUT and COMMOUT buffers powerdown

1500

Pulse duration, all others unspecified

10

ns

(1)

(2)

All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching

90% of transition.

(3)

Quiet time zones are for meeting performance and not functionality.

All specifications typical at –40

PARAMETER

MIN

TYP

MAX

UNIT

CONVERSION AND ACQUISITION

Conversion time, internal to device, not externally visible

180

ns

Delay time, CONVST fall to conversion start (aperture delay)

3

ns

DATA READ OPERATION

Delay time, CONVST low to data valid if CS = RD = 0

225

ns

Delay time, data valid to BUSY low if CS = RD = 0

5

ns

Delay time, RD (or CS) low to data valid

17

ns

Delay time, BYTE toggle to data valid

20

ns

Delay time, data three-state after RD (or CS) high

12

ns

POWER DOWN

Delay time, PD1 low to BUSY rising

20

ns

Delay time, PD1 high to device operational (with PD2 held high)

5

µs

Delay time, PD2 high to REFOUT/COMMOUT valid

25

ms

25

ms

Delay time, data three-state after PD1 low

1.5

µs

(1)

(2)

All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching

90% of transition.

6

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