AM1705DPTP3 datasheet(101/165 Pages) TI1

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AM1705

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SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

6.17.2 SPI Electrical Data/Timing

6.17.2.1 Serial Peripheral Interface (SPI) Timing

Table 6-49 through Table 6-64 assume testing over recommended operating conditions (see Figure 6-33

through Figure 6-36).

Table 6-49. General Timing Requirements for SPI0 Master Modes(1)

No.

PARAMETER

MIN

MAX

UNIT

tc(SPC)M

Cycle Time, SPI0_CLK, All Master Modes

greater of 3P or 20

256P

tw(SPCH)M

Pulse Width High, SPI0_CLK, All Master Modes

0.5tc(SPC)M - 1

tw(SPCL)M

Pulse Width Low, SPI0_CLK, All Master Modes

0.5tc(SPC)M - 1

Polarity = 0, Phase = 0,

to SPI0_CLK rising

Polarity = 0, Phase = 1,

- 0.5tc(SPC)M + 5

Delay, initial data bit valid on

to SPI0_CLK rising

td(SIMO_SPC)M

SPI0_SIMO after initial edge

Polarity = 1, Phase = 0,

on SPI0_CLK(2)

to SPI0_CLK falling

Polarity = 1, Phase = 1,

- 0.5tc(SPC)M + 5

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid

from SPI0_CLK falling

td(SPC_SIMO)M

on SPI0_SIMO after transmit

Polarity = 1, Phase = 0,

edge of SPI0_CLK

from SPI0_CLK falling

Polarity = 1, Phase = 1,

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)M - 3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

0.5tc(SPC)M - 3

Output hold time, SPI0_SIMO

from SPI0_CLK rising

toh(SPC_SIMO)M

valid afterreceive edge of

Polarity = 1, Phase = 0,

SPI0_CLK

0.5tc(SPC)M - 3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)M - 3

from SPI0_CLK falling

Polarity = 0, Phase = 0,

to SPI0_CLK falling

Polarity = 0, Phase = 1,

Input Setup Time, SPI0_SOMI

to SPI0_CLK rising

tsu(SOMI_SPC)M

valid beforereceive edge of

Polarity = 1, Phase = 0,

SPI0_CLK

to SPI0_CLK rising

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time, SPI0_SOMI

from SPI0_CLK rising

tih(SPC_SOMI)M

valid after

Polarity = 1, Phase = 0,

receive edge of SPI0_CLK

from SPI0_CLK rising

Polarity = 1, Phase = 1,

from SPI0_CLK falling

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on

SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.

Peripheral Information and Electrical Specifications

101

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