AM1705DPTP3 datasheet(103/165 Pages) TI1

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AM1705

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SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

Table 6-51. Additional(1) SPI0 Master Timings, 4-Pin Enable Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

3P + 3.6

to SPI0_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 3P + 3.6

Delay from slave assertion of

to SPI0_CLK rising

td(ENA_SPC)M

SPI0_ENA active to first SPI0_CLK

Polarity = 1, Phase = 0,

from master.(4)

3P + 3.6

to SPI0_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 3P + 3.6

to SPI0_CLK falling

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P + 5

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Max delay for slave to deassert

P + 5

from SPI0_CLK falling

SPI0_ENA after final SPI0_CLK edge

td(SPC_ENA)M

to ensure master does not begin the

Polarity = 1, Phase = 0,

0.5tc(SPC)M + P + 5

next transfer.(5)

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P + 5

from SPI0_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes (Table 6-49).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI0_ENA assertion.

(5)

In the case where the master SPI is ready with new data before SPI0_EN A deassertion.

Table 6-52. Additional(1) SPI0 Master Timings, 4-Pin Chip Select Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

2P - 5

to SPI0_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 2P - 5

to SPI0_CLK rising

Delay from SPI0_SCS active to first

td(SCS_SPC)M

SPI0_CLK(4) (5)

Polarity = 1, Phase = 0,

2P - 5

to SPI0_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 2P - 5

to SPI0_CLK falling

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P - 3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

P - 3

from SPI0_CLK falling

Delay from final SPI0_CLK edge to

td(SPC_SCS)M

master deasserting SPI0_SCS (6) (7)

Polarity = 1, Phase = 0,

0.5tc(SPC)M + P - 3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P - 3

from SPI0_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes (Table 6-49).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI0_SCS assertion.

(5)

This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(6)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain

asserted.

(7)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

Peripheral Information and Electrical Specifications

103

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