DP83846 datasheet(9/59 Pages) NSC

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1.7 Reset

1.8 Power and Ground Pins

RX_ER/PAUSE_EN

S, O, PU

PAUSE ENABLE: This strapping option allows advertise-

ment of whether or not the DTE(MAC) has implemented

both the optional MAC control sublayer and the pause func-

tion as specified in clause 31 and annex 31B of the IEEE

802.3x specification (Full Duplex Flow Control).

When left floating the Auto-Negotiation Advertisement Reg-

ister will be set to 0, indicating that Full Duplex Flow Control

is not supported.

When tied low through a 5 k

Ω, the Auto-Negotiation Adver-

tisement Register will be set to 1, indicating that Full Duplex

Flow Control is supported.

The float/pull-down status of this pin is latched into the Auto-

Negotiation Advertisement Register during Hardware-Re-

set.

CRS/LED_CFG

S, O,

LED CONFIGURATION: This strapping option defines the

polarity and function of the FDPLX LED pin.

See Section 2.3 for further descriptions of this strapping op-

tion.

Signal Name

Type

Pin #

Description

RESET

RESET: Active Low input that initializes or re-initializes the

DP83846A. Asserting this pin low for at least 160

µs will

force a reset process to occur which will result in all internal

registers re-initializing to their default states as specified for

each bit in the Register Block section and all strapping op-

tions are re-initialized.

Signal Name

Pin #

Description

TTL/CMOS INPUT/OUTPUT SUPPLY

IO_VDD

35, 43, 57, 65

I/O Supply

IO_GND

34, 42, 53, 56, 64

I/O Ground

INTERNAL SUPPLY PAIRS

CORE_VDD

24, 49, 72

Digital Core Supply

CORE_GND

23, 48, 73

Digital Core Ground

ANALOG SUPPLY PINS

ANA_VDD

4, 7, 12, 14

Analog Supply

ANA_GND

2, 6, 9, 13, 15, 18,

Analog Ground

SUBSTRATE GROUND

SUB_GND

19, 76, 79

Bandgap Substrate connection

Signal Name

Type

Pin #

Description

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