CDCE937-Q1

CDCEL937-Q1

SCAS892B – FEBRUARY 2010 – REVISED MAY 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION

The CDCE937 and CDCEL937 are modular PLL-based low-cost high-performance programmable clock

synthesizers, multipliers, and dividers. It generates up to seven output clocks from a single input frequency. Each

output can be programmed in-system for any clock frequency up to 230 MHz, using up to three independent

configurable PLLs.

The CDCx937 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL937 and to 2.5 V to 3.3 V for

CDCE937.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load

capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.

Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external

control signal, that is, PWM signal.

The deep M/N divider ratio allows the generation of zero ppm audio/video, networking (WLAN, BlueTooth,

Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency such as

27 MHz.

All PLLs supports SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking which

is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically

adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.

The device supports non-volatile EEPROM programming for ease-customized application. It is preset to a factory

default configuration (see the Default Device Configuration section). It can be reprogrammed to a different

application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings

are programmable through SDA/SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including

frequency selection changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing

between low level or 3-state for output-disable function.

The CDCEx937 operates in 1.8-V environment. It is characterized for operation from –40°C to 125°C.

ORDERABLE PART NUMBER

TOP-SIDE MARKING

CDCE937QPWRQ1

CDCE937Q

–40°C to 125°C

TSSOP – PW

Reel of 2000

CDCEL937QPWRQ1

CEL937Q

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

2

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Product Folder Link(s): CDCE937-Q1