CDCE937 datasheet(14/30 Pages) TI1

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SCL

SDA

VIH

VIL

VIH

VIL

Bit7(MSB)

Bit6

Bit0(LSB)

tw(SCLL)

tw(SCLH)

tsu(START)

th(START)

tsu(SDA)

th(SDA)

t(BUS)

tsu(STOP)

SDA

SCL

Master

Slave

CDCE937

CDCEL937

BUS

CDCE937-Q1

CDCEL937-Q1

SCAS892B – FEBRUARY 2010 – REVISED MAY 2010

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Timing Diagram for the SDA/SCL Serial Control Interface

Figure 12. Timing Diagram for SDA/SCL Serial Control Interface

SDA/SCL HARDWARE INTERFACE

Figure 13 shows how the CDCE937/CDCEL937 clock synthesizer is connected to the SDA/SCL serial interface

bus. Multiple devices can be connected to the bus but the speed may need to be reduced (400 kHz is the

maximum) if many devices are connected.

Note that the pullup resistors (RP) depends on the supply voltage, bus capacitance, and number of connected

devices. The recommended pullup value is 4.7 k

Ω. It must meet the minimum sink current of 3 mA at VOLmax =

0.4 V for the output stages (for more details see SMBus or I2C Bus specification).

Figure 13. SDA / SCL Hardware Interface

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CDCE937 Datasheet(PDF) 14 Page - Texas Instruments