CDCE937-Q1

CDCEL937-Q1

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SCAS892B – FEBRUARY 2010 – REVISED MAY 2010

RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS

(1)

MIN

NOM

MAX

UNIT

Crystal input frequency range (fundamental mode)

8

27

32

MHz

ESR

Effective series resistance

100

Ω

Pulling range (0 V

±120

±150

ppm

Frequency control voltage, Vctrl

0

V

Pullability ratio

220

On-chip load capacitance at Xin and Xout

0

20

pF

(1)

For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).

(2)

Pulling range depends on crystal-type, on-chip crystal load capacitance and PCB stray capacitance; pulling range of min ±120 ppm

applies for crystal listed in the application report (SCAA085).

EEPROM SPECIFICATION

MIN

TYP

MAX

UNIT

EEcyc

Programming cycles of EEPROM

1000

cycles

EEret

Data retention

10

years

CLK_IN TIMING REQUIREMENTS

over recommended ranges of supply voltage, load, and operating ambient temperature

MIN

NOM

MAX

UNIT

PLL bypass mode

0

160

LVCMOS clock input frequency

MHz

PLL mode

8

160

Rise and fall time CLK signal (20% to 80%)

3

ns

40%

60%

SDA/SCL TIMING REQUIREMENTS

see Figure 12

STANDARD

FAST

MODE

MODE

UNIT

MIN

MAX

MIN

MAX

SCL clock frequency

0

100

0

400

kHz

START setup time (SCL high before SDA low)

4.7

0.6

ms

START hold time (SCL low after SDA low)

4

0.6

ms

SCL low-pulse duration

4.7

1.3

ms

SCL high-pulse duration

4

0.6

ms

SDA hold time (SDA valid after SCL low)

0

3.45

0

0.9

ms

SDA setup time

250

100

ns

SCL/SDA input rise time

1000

300

ns

SCL/SDA input fall time

300

300

ns

STOP setup time

4

0.6

ms

Bus free time between a STOP and START condition

4.7

1.3

ms

Copyright © 2010, Texas Instruments Incorporated

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