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DP83858VF Datasheet(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83858VF
Description  100 Mb/s TX/T4 Repeater Interface Controller (100RIC8??
PDF  37 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83858VF Datasheet(HTML) 9 Page - National Semiconductor (TI)

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2.4 Miscellaneous
Signal Name
Type
Active
Pin Description
LCK
I
—
Local Clock: Must be 25 MHz
± 50ppm. Used for TX data transfer to Physical Layer
devices, TX Bus data transfers and DP83858 internal state machines.
RID[4:0]
I
—
Repeater Identification Number: Provides the unique vector for the IR_VECT[4:0]
signals used in Inter Repeater bus arbitration. These bit are also used to uniquely iden-
tify this chip for serial register accesses. The RID value is latched when reset is de-
asserted.
Note: The arbiter cannot use the value 1Fh as its arbitration vector. This is the
IR_VECT[4:0] bus idle state, therefore RID[4:0] must never be set to this value.
/RST
I
low
Reset: The chip is reset when this signal is asserted low.
GRDIO
I/O/Z, L
—
Gated Register Data Input/Output: This I/O is a gated version of RDIO. When the
“phy_access” bit in the CONFIG register is set high, the RDIO signal is passed through
to GRDIO for accessing the physical layer chips.
Note: Input buffer has a weak pull-up.
BRDC
O, L
—
Buffered Register Data Clock: Buffered version of RDC. Allows more devices to be
chained on the MII serial bus.
RDIR
O, L
high
Register Data Direction: Direction signal for an external bi-directional buffer on the
RDIO signal.
0
= RDIO data flows into the DP83858
1
= RDIO data flows out of the DP83858
Defaults to 0 when no register access is present.
PART[5:0]
O, L
—
Partition: Used to indicate each port's Jabber and Partition status. PART[3:0] cycle
through each port number (0-11) continuously. PART[4] indicates the Partition status
for each port (1 = Port Partitioned). PART[5] indicates the Jabber status for each port
(1 = Port Jabbering). These pins are intended to be decoded to drive LEDs.
RID_ER
O, L
high
Repeater ID Error: This pin is asserted under the conditions which set the RID_error
bit in the DEVICEID register.
RSM[3]
/RXECONFIG
I/O, L
—
Repeater State Machine Output/ RXE Polarity: This pin is an input during reset and
it is used to latch the desired polarity of RXE[7:0] signals.
When this pin is pulled high or it is unconnected, then the RXE signals become active
high. However, if this signal is pulled low, then the RXE signals become active low.
In all other non-reset times, this pin reflects the output of the Repeater State Machine.
RSM[3]
RSM[2:0]
I/O, L O, L
—
Test Outputs indicating the state of the Repeater State Machine.
RSM[3:0]
State
0
idle
1
collision
2
one port left
3
repeat
4
noise
Other states are undefined.
MODE[1:0]
I
—
Mode Inputs: The 100RIC8 may be configured in the following modes:
MODE[1:0]
Operation
0,0
No special modes selected
1,0
Test mode
0,1
Test mode
1,1
Preamble regeneration (T4) mode
Note: A table showing pin type designation is given in section 2.5



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