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4.0 Registers

The DP83858 has 64 registers in 2 pages of 32 16-bit registers. At power-on and/or reset, the DP83858 defaults to Page

0 registers. The register page can be changed by writing to the PAGE register in either register page. The register page

maps are given in sections 4.1 and 4.2, followed by a detailed description of the registers in sections 4.3 to 4.12.

4.1 Page 0 Register Map

4.2 Page 1 Register Map

Address

(hex)

Name

Access

Description

0

CONFIG

r/w

Sets the DP83858 configuration.

1

PAGE

r/w

Selects either register page 0 or 1.

2

PARTITION read only Indicates Auto-Partitioning status.

3

JABBER

read only Indicates Jabber status.

4

ADMIN

r/w

Port enable/disable, administration control/status.

5

DEVICEID

r/w

Accesses a) the DP83858 ID number configured externally on the RID[4:0] pins and

b) the last receiving port number. The DP83858 device number may be overwritten af-

ter it has been latched at the end of reset: be careful not to have duplicate ID’s on the

same IR bus interface.

6

HUBID0

read only First 16 bits read from EEPROM.

7

HUBID1

read only Second 16 bits read from EEPROM.

8

P0_SE

r/w

Port 0: 32-bit ShortEvent counter (See access rules section 4.11).

9

P0_LE

r/w

Port 0: 32-bit LateEvent counter (See access rules section 4.11).

A

P0_COL

r/w

Port 0: 32-bit Collision counter (See access rules section 4.11).

B

P0_PART

r/w

Port 0: 16-bit Auto-Partition counter.

C

P1_SE

r/w

Port 1: 32-bit ShortEvent counter (See access rules section 4.11).

D

P1_LE

r/w

Port 1: 32-bit LateEvent counter (See access rules section 4.11).

E

P1_COL

r/w

Port 1: 32-bit Collision counter (See access rules section 4.11).

F

P1_PART

r/w

Port 1: 16-bit Auto-Partition counter.

10 - 13

P2_SE ...

P2_PART

r/w

Port 2 management counters (as per ports 0, 1 above).

14 - 17

P3_SE ...

P3_PART

r/w

Port 3 management counters (as per ports 0, 1 above).

18 - 1B

P4_SE ...

P4_PART

r/w

Port 4 management counters (as per ports 0, 1 above).

1C - 1F

P5_SE ...

P5_PART

r/w

Port 5 management counters (as per ports 0, 1 above).

Address

(hex)

Name

Access

Description

0

CONFIG

r/w

Sets the DP83858 configuration (same as page 0 CONFIG register).

1

PAGE

r/w

Select either register page 0 or 1.

2

-

—

Reserved

3

-

—

Reserved

4

SIREV

read only Silicon revision code.

5 - 7

-

—

Reserved

8 - B

P6_SE ...

P6_PART

r/w

Port 6 management counters (as per ports 0, 1 above).

C - F

P7_SE ...

P7_PART

r/w

Port 7 management counters (as per ports 0, 1 above).